Patent US5994676A successfully refreshed from Google Patents.
US5994676A
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Method for calibrating the temperature of an epitaxy reactor
Assignee: STMicroelectronics SA
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Filing: 1997-01-30
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Granted: 1999-11-30
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Expires: 2017-01-30
Abstract
Abstract A method for calibrating the temperature of an epitaxy reactor includes the steps of preparing a reference wafer having undergone on at least one of its surfaces an implant of a doping followed by an activation annealing to form a diffused layer; measuring the sheet resistance of the diffused layer at one point on the surface of the wafer; placing the reference wafer in the epitaxy reactor, the reactor being set at a desired temperature and having a neutral gas flowing therein; and measuring the sheet resistance at the same point and calculating the difference between the two values of sheet resistance, this difference representing the thermal cycle undergone by the reference wafer during its stay in the epitaxy reactor.
Inventors
- 👤 Didier Dutartre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:23
CPC Classifications
C; C23; C23C; C23C16/00; C23C16/44; C23C16/46; C30; C30B; C30B25/00; C30B25/02; C30B25/10
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
181 words
A method for verifying a temperature of an epitaxy reactor, including the steps of: (a) preparing a reference wafer of mono-crystalline silicon having undergone on at least one surface an implant of a doping element followed by an activation annealing to form a diffused layer; (b) measuring a first sheet resistance of the diffused layer at at least one location on the at least one surface of the reference wafer being at a first test temperature; (c) placing the reference wafer in the epitaxy reactor, the epitaxy reactor being set at a desired temperature using a heating system, and having a neutral gas flowing therein; (d) measuring a second sheet resistance at the at least one location on the at least one surface of the reference wafer being at a second test temperature and calculating a relationship between the first sheet resistance and the second sheet resistance, the relationship being related to a thermal cycle undergone by the reference wafer during its stay in the epitaxy reactor; and (e) verifying the desired temperature of the heating system based on the relationship.
Claim 2
Independent Claim
181 words
A method for verifying a temperature of an epitaxy reactor, including the steps of: (a) preparing a reference wafer of mono-crystalline silicon having undergone on at least one surface an implant of a doping element followed by an activation annealing to form a diffused layer; (b) measuring a first sheet resistance of the diffused layer at at least one location on the at least one surface of the reference wafer being at a first test temperature; (c) placing the reference wafer in the epitaxy reactor, the epitaxy reactor being set at a desired temperature using a heating system, and having a neutral gas flowing therein; (d) measuring a second sheet resistance at the at least one location on the at least one surface of the reference wafer being at a second test temperature and calculating a relationship between the first sheet resistance and the second sheet resistance, the relationship being related to a thermal cycle undergone by the reference wafer during its stay in the epitaxy reactor; and (e) verifying the desired temperature of the heating system based on the relationship.
Claim 3
Dependent Claim
22 words
The method according to claim 1, wherein the reference wafer undergoes an activation annealing and a drive-in annealing in an oxidizing atmosphere.
Claim 4
Dependent Claim
26 words
The method according to claim 1, wherein the reference wafer is of a first conductivity type and the diffused layer is of a second conductivity type.
Claim 5
Dependent Claim
22 words
The method according to claim 3, wherein the reference wafer is a lightly doped P-type wafer and the doping element includes arsenic.
Claim 6
Dependent Claim
79 words
The method according to claim 1, further including measuring at least one of the first and second sheet resistance at a plurality of locations on the reference wafer, and determining a difference of the sheet resistances between at least two of the plurality of locations on the reference wafer, variations between the determined differences for the plurality of locations being related to a temperature differences over the plurality of locations during the thermal cycle undergone by the reference wafer.
Claim 7
Dependent Claim
34 words
The method according to claim 1 further including the step of adjusting a setting of the heating system for heating the epitaxy reactor responsive to the relationship between the first and second sheet resistances.
Claim 8
Dependent Claim
57 words
The method according to claim 5 further including the step of adjusting a setting of the heating system for heating the epitaxy reactor responsive to the variations between the differences between the sheet resistances measured for the plurality of locations to obtain selected values of the temperature difference for the plurality of locations during the thermal cycle.
Claim 9
Dependent Claim
16 words
The method according to claim 1, wherein the first and second test temperatures are approximately equal.
Claim 10
Dependent Claim
22 words
The method according to claim 7, wherein the selected values of the temperature difference for the plurality of locations are approximately zero.
Claim 11
Independent Claim
122 words
A method for calibrating an operating parameter of a semiconductor processing device, including the steps of: measuring a first value of an electrical property of at least one portion of a semiconductor wafer being at a first test temperature; placing the wafer in the processing device, the operating parameter of the processing device being set to a particular value; measuring a second value of the electrical property of the at least one portion of the wafer being at a second test temperature; calculating a relationship between the first value and the second value of the electrical property; and responsive to the relationship between the first value and the second value of the electrical property, determining a proper calibration of the operating parameter.
Claim 12
Independent Claim
122 words
A method for calibrating an operating parameter of a semiconductor processing device, including the steps of: measuring a first value of an electrical property of at least one portion of a semiconductor wafer being at a first test temperature; placing the wafer in the processing device, the operating parameter of the processing device being set to a particular value; measuring a second value of the electrical property of the at least one portion of the wafer being at a second test temperature; calculating a relationship between the first value and the second value of the electrical property; and responsive to the relationship between the first value and the second value of the electrical property, determining a proper calibration of the operating parameter.
Claim 13
Dependent Claim
99 words
The method according to claim 10, wherein: the step of measuring the first value of the electrical property includes measuring a first resistance at a particular location on a surface of a diffused layer included in the wafer; the step of measuring the second value of the electrical property includes the step of measuring a second resistance at the particular location on the surface of the diffused layer; and the step of calculating the relationship between the first value and the second value of the electrical property includes calculating a relationship between the first resistance and the second resistance.
Claim 14
Dependent Claim
61 words
The method according to claim 11, wherein: the step of placing the wafer in the processing device includes placing the wafer in a epitaxy reactor, the reactor being set to heat the wafer to a particular temperature; and the step of determining the proper calibration of the operating parameter includes determining the proper calibration of a temperature setting of the reactor.
Claim 15
Dependent Claim
61 words
The method according to claim 10, wherein: the step of placing the wafer in the processing device includes placing the wafer in an epitaxy reactor, the reactor being set to heat the wafer to a particular temperature; and the step of determining the proper calibration of the operating parameter includes determining the proper calibration of a temperature setting of the reactor.
Claim 16
Dependent Claim
25 words
The method according to claim 13, further comprising the step of adjusting the temperature setting of the reactor according to the determined proper calibration thereof.
Claim 17
Dependent Claim
39 words
The method according to claim 14, wherein the step of adjusting the temperature setting of the reactor includes adjusting a setting of at least one heating device included in a plurality of heating devices arranged to heat the wafer.
Claim 18
Dependent Claim
22 words
The method according to claim 10, further comprising the step of adjusting the operating parameter according to the determined proper calibration thereof.
Claim 19
Dependent Claim
60 words
The method according to claim 10, further comprising the step of preparing the wafer prior to measuring the electrical property of the at least one portion thereof, by performing the steps of: implanting a doping element into at least one surface of a mono-crystalline wafer; and annealing the mono-crystalline wafer implanted with the doping element to form a diffused layer.
Claim 20
Dependent Claim
16 words
The method according to claim 10, wherein the first and second test temperatures are approximately equal.
Claim 21
Independent Claim
141 words
A system for verifying a temperature of an epitaxy reactor, comprising a reference semiconductor wafer including a conductive layer; a device constructed and arranged to measure a first sheet resistance of the layer at at least one location of the reference wafer being at a first test temperature, said device being arranged to measure a second sheet resistance at the at least one location of the reference wafer being at a second test temperature after undergoing a thermal cycle inside of the epitaxy reactor; and a processor constructed and arranged to calculate a relationship between the first sheet resistance and the second sheet resistance, the relationship being related to the thermal cycle undergone by the reference wafer, said processor being arranged to provide the relationship to the epitaxy reactor for verifying the desired temperature of a heating system of the reactor.
Claim 22
Independent Claim
141 words
A system for verifying a temperature of an epitaxy reactor, comprising a reference semiconductor wafer including a conductive layer; a device constructed and arranged to measure a first sheet resistance of the layer at at least one location of the reference wafer being at a first test temperature, said device being arranged to measure a second sheet resistance at the at least one location of the reference wafer being at a second test temperature after undergoing a thermal cycle inside of the epitaxy reactor; and a processor constructed and arranged to calculate a relationship between the first sheet resistance and the second sheet resistance, the relationship being related to the thermal cycle undergone by the reference wafer, said processor being arranged to provide the relationship to the epitaxy reactor for verifying the desired temperature of a heating system of the reactor.
Claim 23
Dependent Claim
14 words
The system claim 19, wherein the first and second test temperatures are approximately equal.
Claim 24
Dependent Claim
37 words
The system of claim 19 wherein the reference wafer is a mono-crystalline silicon wafer having on at least one surface an ion implant of a doping element followed by an activation annealing to form a diffused layer.
Claim 25
Dependent Claim
82 words
The system of claim 19 wherein said device is further constructed and arranged to measure at least one of the first and second sheet resistance at a plurality of locations on the reference wafer and determine a difference of the sheet resistance between at least two of the plurality of locations on the reference wafer, the difference for the plurality of locations being related to a temperature difference over the plurality of locations during the thermal cycle undergone by the reference wafer.
Claim 26
Dependent Claim
56 words
The system of claim 22 further constructed and arranged to provide an input for adjusting a setting of a heating system of the epitaxy reactor responsive to the differences between the sheet resistances measured for the plurality of locations to obtain selected values of the temperature difference for the plurality of locations during the thermal cycle.
Claim 27
Dependent Claim
29 words
The system of claim 23 wherein the input is arranged so that the heating system is calibrated to have the selected values of the temperature difference equal to zero.
Claim 28
Independent Claim
124 words
A system for calibrating an operating parameter of a semiconductor processing device, comprising a reference semiconductor wafer including a conductive layer; a device constructed and arranged to measure a first value of an electrical property at at least one portion of the reference wafer, the device being further constructed and arranged to measure a second value of the electrical property at the at least one portion of the reference wafer after the wafer undergoing a selected thermal cycle inside the semiconductor processing device; and a processor constructed and arranged to calculate a relationship between the first value and the second value of the electrical property and provide an input to the semiconductor processing device to calibrate the operating parameter based on the calculated relationship.
Claim 29
Independent Claim
124 words
A system for calibrating an operating parameter of a semiconductor processing device, comprising a reference semiconductor wafer including a conductive layer; a device constructed and arranged to measure a first value of an electrical property at at least one portion of the reference wafer, the device being further constructed and arranged to measure a second value of the electrical property at the at least one portion of the reference wafer after the wafer undergoing a selected thermal cycle inside the semiconductor processing device; and a processor constructed and arranged to calculate a relationship between the first value and the second value of the electrical property and provide an input to the semiconductor processing device to calibrate the operating parameter based on the calculated relationship.
Claim 30
Dependent Claim
26 words
The system of claim 25 wherein the semiconductor processing device includes an epitaxy reactor constructed and arranged to heat the reference wafer to a selected temperature.
Claim 31
Dependent Claim
76 words
The system of claim 26 wherein the device is further constructed and arranged to measure the electrical property over a plurality of locations on the reference wafer and is further arranged to determine a difference of the measured electrical property between at least two of the plurality of locations on the reference wafer and provide the input to the epitaxy reactor to achieve a substantially uniform temperature over the plurality of locations during the thermal cycle.
Claim 32
Dependent Claim
17 words
The system of claim 27 wherein the device is further constructed and arranged to measure sheet resistance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |