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US5994227A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing semiconductor device

Assignee: Renesas Electronics Corp
•
Filing: 1998-07-20
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Granted: 1999-11-30
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Expires: 2018-07-20
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Abstract

Abstract An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH 2 F 2 and O 2 . As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

Inventors

  • 👤 Hiroshi Matsuo
  • 👤 Takuji Oda
  • 👤 Yuichi Yokoyama
  • 👤 Kiyoshi Maeda
  • 👤 Shinya Inoue
  • 👤 Yuji Yamamoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 17:19
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0402; H10P72/0418; H10P72/0421; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/071; H10W20/081

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 189 words
A method of manufacturing a semiconductor device comprising the steps of: forming on a semiconductor substrate a first interconnection pattern and a second interconnection pattern adjacent to each other, each with a first oxide film formed thereon; forming a second oxide film on said semiconductor substrate to cover sidewalls of said first and second interconnection patterns; forming a silicon nitride film as an etching stopper to cover said first and second interconnection patterns with said first and second oxide films interposed therebetween; forming an interlayer insulating film on said semiconductor substrate to cover said silicon nitride film; etching, using a resist pattern, a portion of said interlayer insulating film located between said first interconnection pattern and said second interconnection pattern until a surface of said silicon nitride film is exposed, to form a contact hole; removing said resist pattern; and dry-etching in a self-aligned manner a bottom of said contact hole employing mixed gas plasma containing CH 2 F 2 and O 2 with a mixture ratio of said O 2 to said CH 2 F 2 between 25 and 40%, to expose a surface of said semiconductor substrate.
Claim 2
Independent Claim 189 words
A method of manufacturing a semiconductor device comprising the steps of: forming on a semiconductor substrate a first interconnection pattern and a second interconnection pattern adjacent to each other, each with a first oxide film formed thereon; forming a second oxide film on said semiconductor substrate to cover sidewalls of said first and second interconnection patterns; forming a silicon nitride film as an etching stopper to cover said first and second interconnection patterns with said first and second oxide films interposed therebetween; forming an interlayer insulating film on said semiconductor substrate to cover said silicon nitride film; etching, using a resist pattern, a portion of said interlayer insulating film located between said first interconnection pattern and said second interconnection pattern until a surface of said silicon nitride film is exposed, to form a contact hole; removing said resist pattern; and dry-etching in a self-aligned manner a bottom of said contact hole employing mixed gas plasma containing CH 2 F 2 and O 2 with a mixture ratio of said O 2 to said CH 2 F 2 between 25 and 40%, to expose a surface of said semiconductor substrate.
Claim 3
Dependent Claim 27 words
The method of manufacturing a semiconductor device according to claim 1, wherein said etching is conducted to form a bit line contact of a memory cell portion.
Claim 4
Dependent Claim 27 words
The method of manufacturing a semiconductor device according to claim 1, wherein said etching is conducted to form a storage node contact of a memory cell portion.
Claim 5
Dependent Claim 33 words
The method of manufacturing a semiconductor device according to claim 1, wherein an opening formed in said resist pattern for formation of said contact hole has a diameter of 0.1 to 0.5 μm.
Claim 6
Independent Claim 207 words
A method of manufacturing a semiconductor device, comprising the steps of: forming on a semiconductor substrate a first interconnection pattern and a second interconnection pattern adjacent to each other, each with a first oxide film formed thereon; forming a second oxide film on said semiconductor substrate to cover sidewalls of said first and second interconnection patterns; forming a silicon nitride film as an etching stopper to cover said first and second interconnection patterns with said first and second oxide films interposed therebetween; forming an interlayer insulating film on said semiconductor substrate to cover said silicon nitride film; etching, using a resist pattern, a portion of said interlayer insulating film located between said first interconnection pattern and said second interconnection pattern until a surface of said silicon nitride film is exposed, to form a contact hole; removing said resist pattern; etching said silicon nitride film at a bottom of said contact hole in a self-aligned manner to expose a surface of said second oxide film; and etching said second oxide film at the bottom of said contact hole in a self-aligned manner by setting etch selectivity of said first oxide film to said silicon nitride film to at most 1, to expose a surface of said semiconductor substrate.
Claim 7
Independent Claim 207 words
A method of manufacturing a semiconductor device, comprising the steps of: forming on a semiconductor substrate a first interconnection pattern and a second interconnection pattern adjacent to each other, each with a first oxide film formed thereon; forming a second oxide film on said semiconductor substrate to cover sidewalls of said first and second interconnection patterns; forming a silicon nitride film as an etching stopper to cover said first and second interconnection patterns with said first and second oxide films interposed therebetween; forming an interlayer insulating film on said semiconductor substrate to cover said silicon nitride film; etching, using a resist pattern, a portion of said interlayer insulating film located between said first interconnection pattern and said second interconnection pattern until a surface of said silicon nitride film is exposed, to form a contact hole; removing said resist pattern; etching said silicon nitride film at a bottom of said contact hole in a self-aligned manner to expose a surface of said second oxide film; and etching said second oxide film at the bottom of said contact hole in a self-aligned manner by setting etch selectivity of said first oxide film to said silicon nitride film to at most 1, to expose a surface of said semiconductor substrate.
Claim 8
Dependent Claim 27 words
The method of manufacturing a semiconductor device according to claim 5, wherein said etching is conducted to form a bit line contact of a memory cell portion.
Claim 9
Dependent Claim 27 words
The method of manufacturing a semiconductor device according to claim 5, wherein said etching is conducted to form a storage node contact of a memory cell portion.
Claim 10
Independent Claim 190 words
A method of manufacturing a semiconductor device, comprising the steps of: forming on a semiconductor substrate a first interconnection pattern and a second interconnection pattern adjacent to each other, each with a first oxide film formed thereon; forming a second oxide film on said semiconductor substrate to cover both sidewalls of both of said first and second interconnection patterns; forming sidewall spacers made of a third oxide film on the both sidewalls of said first interconnection pattern and the both sidewalls of said second interconnection pattern; forming a silicon nitride film as an etching stopper to cover said first and second interconnection patterns with said first, second and third oxide films interposed therebetween; forming an interlayer insulating film on said semiconductor substrate to cover said silicon nitride film; etching, using a resist pattern, a portion of said interlayer insulating film located between said first interconnection pattern and said second interconnection pattern until a surface of said silicon nitride film is exposed, to form a contact hole; removing said resist pattern; and etching a bottom of said contact hole in a self-aligned manner to expose a surface of said semiconductor substrate.
Claim 11
Independent Claim 190 words
A method of manufacturing a semiconductor device, comprising the steps of: forming on a semiconductor substrate a first interconnection pattern and a second interconnection pattern adjacent to each other, each with a first oxide film formed thereon; forming a second oxide film on said semiconductor substrate to cover both sidewalls of both of said first and second interconnection patterns; forming sidewall spacers made of a third oxide film on the both sidewalls of said first interconnection pattern and the both sidewalls of said second interconnection pattern; forming a silicon nitride film as an etching stopper to cover said first and second interconnection patterns with said first, second and third oxide films interposed therebetween; forming an interlayer insulating film on said semiconductor substrate to cover said silicon nitride film; etching, using a resist pattern, a portion of said interlayer insulating film located between said first interconnection pattern and said second interconnection pattern until a surface of said silicon nitride film is exposed, to form a contact hole; removing said resist pattern; and etching a bottom of said contact hole in a self-aligned manner to expose a surface of said semiconductor substrate.
Claim 12
Dependent Claim 27 words
The method of manufacturing a semiconductor device according to claim 8, wherein said etching is conducted to form a bit line contact of a memory cell portion.
Claim 13
Dependent Claim 27 words
The method of manufacturing a semiconductor device according to claim 8, wherein said etching is conducted to form a storage node contact of a memory cell portion.

References Cited (Backward Citations)

US5462896A Cited
US5286344A Cited
JPH0612765A Cited
JPH07161702A Cited
JPH0897186A Cited
US5726100A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-11-29 2003-05-31 2003-11-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-11-29 2007-05-31 2007-11-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-11-29 2011-05-31 2011-11-30 $7700.00 Window Closed / Lapsed

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