Method of forming contact vias and interconnect channels in a dielectric layer stack with a single mask

Claim 2

A process for forming contact vias and interconnect channels in a dielectric layer stack having a lower dielectric layer, an upper dielectric layer, and a primary dielectric etch stop layer sandwiched between the upper and lower dielectric layers, said process comprising the steps of: (a) forming a photomask on an upper surface of the upper dielectric layer, said photomask having a first set of apertures defining a contact via pattern, each aperture of the first set having a corresponding first critical dimension, said photomask also having a second set of apertures defining an interconnect channel pattern having both linear segments and at least one curved segment which interconnects a pair of linear segments, each linear segment and each curved segment of each aperture of the second set having a corresponding second critical dimension that is less than said first critical dimension; (b) performing a first etch that is selective for the first dielectric layer over the primary etch stop layer, said first etch continuing until selected first portions of the primary etch stop layer are exposed below each aperture of said first set, but before selected second portions of the primary etch stop layer are exposed below any aperture of said second set; (c) removing said first portions of the primary etch stop layer; and (d) performing a second etch that is selective for both the upper dielectric layer and the lower dielectric layer over the primary etch stop layer, said second etch proceeding until said second portions of the primary etch stop layer are exposed and until the lower dielectric layer is perforated below each aperture of said first set.

Claim 3

The process of claim 1, wherein both said first and second etches are reactive-ion etches.

Claim 4

The process of claim 2, wherein exposure of the selected first portions of the primary etch stop layer is detected by monitoring an emitted energy level during the first reactive-ion etch.

Claim 5

The process of claim 1, wherein said dielectric layer stack also has a secondary dielectric etch stop layer subjacent and in contact with the lower dielectric layer, said secondary etch stop layer overlying conductive regions, to each of which electrical contact must be made through a contact via.

Claim 6

The process of claim 4, wherein a selected portion of the secondary etch stop layer is exposed at the bottom of each contact via as the lower dielectric layer is perforated, and the process further comprises the step of removing said selected portion of the secondary etch stop layer at the bottom of each contact via and said second portions of the primary etch stop layer following the second etch.

Claim 7

The process of claim 5, wherein exposure of the selected portions of the secondary etch stop layer is detected by monitoring an emitted energy level during the second reactive-ion etch.

Claim 8

The process of claim 4, wherein, compositionally, said primary and secondary etch stop layers are predominantly silicon nitride.

Claim 9

The process of claim 4 wherein removal of said selected portion of the secondary etch stop layer at the bottom of each contact via and said second portions of the primary etch stop layer is accomplished with a reactive-ion etch that is selective for the both the primary and the secondary etch stop layers over the upper and lower dielectric layers.

Claim 10

The process of claim 1 wherein, compositionally, the upper and lower dielectric layers are predominantly silicon dioxide.

Claim 11

The process of claim 1, wherein said first portions of the primary etch stop layer are removed with a reactive-ion etch that is selective for the primary etch stop layer over the upper dielectric layer.

Claim 12

A process for forming both a vertically-oriented contact via, which extends from an upper level of an integrated circuit to a conductive region at a lower level within the circuit, and an interconnect channel having both linear segments and at least one curved segment joining a pair of linear segments within the upper level of the circuit, said channel being continuous with an upper portion of said via, said process comprising the steps of: (a) depositing a lower dielectric layer over the conductive regions; (b) depositing a primary dielectric etch stop layer above the lower dielectric layer; (c) depositing an upper dielectric layer above the primary etch stop layer; (d) forming a photomask on an upper surface of the upper dielectric layer, said photomask having a first aperture defining a pattern for said contact via, said first aperture having a first critical dimension, said photomask also having a second aperture defining a pattern for said interconnect channel, said second aperture having both linear segments and at least one curved segment which interconnects a pair of linear segments, each of said linear segments and said curved segment having a second critical dimension that is less than said first critical dimension; (e) performing a first etch that is selective for the first dielectric layer over the primary etch stop layer, said first etch continuing until selected first portions of the primary etch stop layer are exposed below each aperture of said first set, but before selected second portions of the primary etch stop layer are exposed below apertures of said second set; (f) removing said first portions of the primary etch stop layer; (g) performing a second etch that is selective for both the upper dielectric layer and the lower dielectric layer over the primary etch stop layer, said second etch proceeding until said second portions of the primary etch stop layer are exposed and until the lower dielectric layer is perforated below each aperture of said first set; and (h) removing the photomask.

Claim 13

A process for forming both a vertically-oriented contact via, which extends from an upper level of an integrated circuit to a conductive region at a lower level within the circuit, and an interconnect channel having both linear segments and at least one curved segment joining a pair of linear segments within the upper level of the circuit, said channel being continuous with an upper portion of said via, said process comprising the steps of: (a) depositing a lower dielectric layer over the conductive regions; (b) depositing a primary dielectric etch stop layer above the lower dielectric layer; (c) depositing an upper dielectric layer above the primary etch stop layer; (d) forming a photomask on an upper surface of the upper dielectric layer, said photomask having a first aperture defining a pattern for said contact via, said first aperture having a first critical dimension, said photomask also having a second aperture defining a pattern for said interconnect channel, said second aperture having both linear segments and at least one curved segment which interconnects a pair of linear segments, each of said linear segments and said curved segment having a second critical dimension that is less than said first critical dimension; (e) performing a first etch that is selective for the first dielectric layer over the primary etch stop layer, said first etch continuing until selected first portions of the primary etch stop layer are exposed below each aperture of said first set, but before selected second portions of the primary etch stop layer are exposed below apertures of said second set; (f) removing said first portions of the primary etch stop layer; (g) performing a second etch that is selective for both the upper dielectric layer and the lower dielectric layer over the primary etch stop layer, said second etch proceeding until said second portions of the primary etch stop layer are exposed and until the lower dielectric layer is perforated below each aperture of said first set; and (h) removing the photomask.

Claim 14

The process of claim 11, wherein said first and second etches are reactive-ion etches.

Claim 15

The process of claim 12, wherein exposure of the selected first portions of the primary etch stop layer is detected by monitoring an emitted energy level during the first reactive-ion etch.

Claim 16

The process of claim 11, which further comprises the steps of: (a) depositing a secondary dielectric etch stop layer above the conductive region prior to depositing the lower dielectric layer; (b) exposing a selected portion of the secondary etch stop layer at the bottom of the contact via as the lower dielectric layer is perforated; and (c) removing said selected portion of the secondary etch stop layer and said second portions of the primary etch stop layer after the second etch.

Claim 17

The process of claim 14, wherein exposure of the selected portions of the secondary etch stop layer is detected by monitoring an emitted energy level during the second reactive-ion etch.

Claim 18

The process of claim 11 wherein, compositionally, the upper and lower dielectric layers are predominantly silicon dioxide, and the primary etch stop layer is predominantly silicon nitride.

Claim 19

The process of claim 11, which further comprises the additional process of forming metal structures within said via and said channel, said additional process comprising the steps of: (a) depositing a metal layer stack which fills the contact via and interconnect channel and covers the upper surface of the upper dielectric layer; and (b) removing a selected portion of the metal layer stack which covers the upper surface of the upper dielectric layer so as to leave metal in only the contact via and in the interconnect channel.

Claim 20

A process for forming contact and interconnect structures in a dielectric layer stack having a lower dielectric layer, an upper dielectric layer, and a primary dielectric etch stop layer sandwiched between the upper and lower dielectric layers, said process comprising the steps of: (a) forming a photomask on an upper surface of the upper dielectric layer, said photomask having a first set of apertures defining a contact via pattern, each aperture of the first set having a corresponding first critical dimension, said photomask also having a second set of apertures defining an interconnect channel pattern having both linear segments and at least one curved segment which interconnects a pair of linear segments, each linear segment and each curved segment of each aperture of the second set having a corresponding second critical dimension that is less than said first critical dimension; (b) performing a first etch that is selective for the first dielectric layer over the primary etch stop layer, said first etch continuing until selected first portions of the primary etch stop layer are exposed below each aperture of said first set, but before selected second portions of the primary etch stop layer are exposed below any aperture of said second set; (c) removing said first portions of the primary etch stop layer; (d) performing a second etch that is selective for both the upper dielectric layer and the lower dielectric layer over the primary etch stop layer, said second etch proceeding until said second portions of the primary etch stop layer are exposed and until the lower dielectric layer is perforated below each aperture of said first set; (e) removing the photomask; (f) depositing a metal layer stack which fills the contact vias and interconnect channels and covers the upper surface of the upper dielectric layer; and (g) removing the metal stack which covers the upper surface of the upper dielectric layer so as to leave metal in only the contact vias and in the interconnect channels.

Claim 21

A process for forming contact and interconnect structures in a dielectric layer stack having a lower dielectric layer, an upper dielectric layer, and a primary dielectric etch stop layer sandwiched between the upper and lower dielectric layers, said process comprising the steps of: (a) forming a photomask on an upper surface of the upper dielectric layer, said photomask having a first set of apertures defining a contact via pattern, each aperture of the first set having a corresponding first critical dimension, said photomask also having a second set of apertures defining an interconnect channel pattern having both linear segments and at least one curved segment which interconnects a pair of linear segments, each linear segment and each curved segment of each aperture of the second set having a corresponding second critical dimension that is less than said first critical dimension; (b) performing a first etch that is selective for the first dielectric layer over the primary etch stop layer, said first etch continuing until selected first portions of the primary etch stop layer are exposed below each aperture of said first set, but before selected second portions of the primary etch stop layer are exposed below any aperture of said second set; (c) removing said first portions of the primary etch stop layer; (d) performing a second etch that is selective for both the upper dielectric layer and the lower dielectric layer over the primary etch stop layer, said second etch proceeding until said second portions of the primary etch stop layer are exposed and until the lower dielectric layer is perforated below each aperture of said first set; (e) removing the photomask; (f) depositing a metal layer stack which fills the contact vias and interconnect channels and covers the upper surface of the upper dielectric layer; and (g) removing the metal stack which covers the upper surface of the upper dielectric layer so as to leave metal in only the contact vias and in the interconnect channels.

Claim 22

The process of claim 18, wherein both first and second etches are reactive-ion etches.

Claim 23

The process of claim 19, wherein exposure of the selected first portions of the primary etch stop layer is detected by monitoring an emitted energy level during the first reactive-ion etch.

Claim 24

The process of claim 18, wherein said dielectric layer stack also has a secondary dielectric etch stop layer below and in contact with the lower dielectric layer, said secondary etch stop layer overlying conductive regions, to each of which electrical contact must be made through a contact via.

Claim 25

The process of claim 21, wherein a selected portion of the secondary etch stop layer is exposed at the bottom of each contact via as the lower dielectric layer is perforated, and the process further comprises the step of removing said selected portion of the secondary etch stop layer at the bottom of each contact via and the other portions of the primary etch stop layer after the second etch step, but before the step of depositing the metal layer.

Claim 26

The process of claim 22, wherein exposure of the selected portions of the secondary etch stop layer is detected by monitoring an emitted energy level during the second reactive-ion etch.

Claim 27

The process of claim 21, wherein, compositionally, said primary and secondary etch stop layers are predominantly silicon nitride.

Claim 28

The process of claim 21 wherein removal of said selected portion of the secondary etch stop layer at the bottom of each contact via and said second portions of the primary etch stop layer is accomplished with a reactive-ion etch that is selective for the primary and secondary etch stop layers over the upper and lower dielectric layers.

Claim 29

The process of claim 18 wherein, compositionally, the upper and lower dielectric layers are predominantly silicon dioxide.

Claim 30

The process of claim 18, wherein said first portions of the primary etch stop layer are removed with a reactive-ion etch that is selective for the primary etch stop layer over the upper dielectric layer.

Claim 31

The process of claim 18 wherein removal of the metal which covers the upper surface of the upper dielectric layer is accomplished with a polishing step.

Claim 32

The process of claim 28, wherein the metal is removed via mechanical abrasion.

Claim 33

The process of claim 28, wherein the metal is removed via mechanical abrasion in combination with chemical dissolution.