Patent US5994009A successfully refreshed from Google Patents.
US5994009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlayer method utilizing CAD for process-induced proximity effect correction
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1997-11-17
•
Granted: 1999-11-30
•
Expires: 2017-11-17
Abstract
Abstract The present invention discloses a novel method for interlayer corrections for photolithographic patterns that are reproduced on a wafer surface capable of correcting not only the optically-induced proximity effect but also the process-induced proximity effect. In the method, a conventional optical proximity correction is first performed on a photomask, the corrected photomask is then used to produce a pattern on a wafer surface. The various critical dimensions bias values at a multiplicity of locations are then measured and fed back to the computer aided design data file for the photomask for producing patterns that are corrected for both optically-induced and process-induced proximity effect on a wafer surface.
Inventors
- 👤 San-De Tzu
- 👤 Shih-Chiang Tu
- 👤 Chia-Hui Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:21
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G03F7/70441; G03F1/00; G03F1/36; G03F9/00; G03F9/70
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
103 words
A method for proximity correction on a wafer surface during a non-electron beam photolithographic process comprising the steps of: providing a computer aided design (CAD) data file containing a photomask pattern, performing an optical proximity correction (OPC) for correcting optically-induced proximity effect, producing a photomask pattern for non-electron beam lithography after the OPC on a pre-processed wafer surface, dividing the wafer surface into a multiplicity of sections, executing a logic method for determining process-induced critical dimension (CD) bias values at each of said multiplicity of sections, and inputting the CD bias values into the CAD data file to correct the process-induced proximity effect.
Claim 2
Independent Claim
103 words
A method for proximity correction on a wafer surface during a non-electron beam photolithographic process comprising the steps of: providing a computer aided design (CAD) data file containing a photomask pattern, performing an optical proximity correction (OPC) for correcting optically-induced proximity effect, producing a photomask pattern for non-electron beam lithography after the OPC on a pre-processed wafer surface, dividing the wafer surface into a multiplicity of sections, executing a logic method for determining process-induced critical dimension (CD) bias values at each of said multiplicity of sections, and inputting the CD bias values into the CAD data file to correct the process-induced proximity effect.
Claim 3
Dependent Claim
25 words
A method according to claim 1, wherein said step of providing a computer aided design data file comprising the step of providing a GDS file.
Claim 4
Dependent Claim
22 words
A method according to claim 1, wherein said pre-processed wafer surface does not require the deposition of a bottom anti-reflectance coating layer.
Claim 5
Dependent Claim
24 words
A method according to claim 1, wherein said pre-processed wafer surface comprising an electrically conductive gate electrode layer deposited on a silicon oxide layer.
Claim 6
Dependent Claim
17 words
A method according to claim 4, wherein said electrically conductive gate electrode layer comprises a polysilicon layer.
Claim 7
Dependent Claim
20 words
A method according to claim 4, wherein said silicon oxide layer comprises thin oxide regions and thick field oxide regions.
Claim 8
Dependent Claim
21 words
A method according to claim 4, wherein said electrically conductive gate electrode layer has a top surface with a substantial topography.
Claim 9
Dependent Claim
48 words
A method according to claim 1, wherein said step of dividing said wafer surface into a multiplicity of sections further comprising the step of dividing said multiplicity of sections on the wafer surface so that surface areas having significant topography differences are included in said multiplicity of sections.
Claim 10
Independent Claim
133 words
A method for correcting a photomask pattern to compensate for process-induced proximity effect during an optical lithography process conducted on a wafer comprising the steps of: providing a computer software for a photomask pattern, modifying the software for optically-induced proximity effect by an optical proximity correction method producing a modified software, providing a wafer having a pre-processed top surface and a topography on said surface, producing a photomask pattern for optical lithograph on the pre-processed top surface of the wafer by aid modified software, dividing the topography on said wafer surface into a multiplicity of sections, determining process-induced critical dimension (CD) bias values at each of said multiplicity of sections, and feeding back said CD bias values of each said multiplicity of sections to said modified software for correcting the process-induced proximity effect.
Claim 11
Independent Claim
133 words
A method for correcting a photomask pattern to compensate for process-induced proximity effect during an optical lithography process conducted on a wafer comprising the steps of: providing a computer software for a photomask pattern, modifying the software for optically-induced proximity effect by an optical proximity correction method producing a modified software, providing a wafer having a pre-processed top surface and a topography on said surface, producing a photomask pattern for optical lithograph on the pre-processed top surface of the wafer by aid modified software, dividing the topography on said wafer surface into a multiplicity of sections, determining process-induced critical dimension (CD) bias values at each of said multiplicity of sections, and feeding back said CD bias values of each said multiplicity of sections to said modified software for correcting the process-induced proximity effect.
Claim 12
Dependent Claim
25 words
A method according to claim 9, wherein said pre-processed top surface of the wafer does not require the deposition of a bottom anti-reflectance coating layer.
References Cited (Backward Citations)
US5254438A
Cited
US5208124A
Cited
US5432714A
Cited
US5667923A
Cited
US5792581A
Cited
US5736281A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |