Method for fabricating a crown-type capacitor of a DRAM cell

Claim 1

A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate, comprising the steps of: (a) forming a transistor including a gate, a drain and a source over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region; (e) successively forming an etching stop layer and a mask layer over the first conducting layer, wherein the etching stop layer and the first conducting layer consist of different materials; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer, for defining a capacitor region; (i) removing the uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.

Claim 2

A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate, comprising the steps of: (a) forming a transistor including a gate, a drain and a source over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region; (e) successively forming an etching stop layer and a mask layer over the first conducting layer, wherein the etching stop layer and the first conducting layer consist of different materials; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer, for defining a capacitor region; (i) removing the uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.

Claim 11

A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate, comprising the steps of: (a) forming a transistor including a gate, a drain and a source over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region; (d) forming a Ti/TiN layer covering the sidewall and bottom of the contact opening, and extending over the insulating layer; (e) forming a tungsten plug in the contact opening; (f) forming a first conducting layer over the exposed Ti/TiN surface, and electrically connecting the tungsten plug; (g) successively forming an etching stop layer and a mask layer over the first conducting layer, wherein the etching stop layer and the first conducting layer consist of different materials; (h) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed; (i) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (j) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the Ti/TiN layer, for defining a capacitor region; (k) removing uncovered Ti/TiN layer and uncovered etching stop layer to expose the first conducting layer; (l) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode including the tungsten plug, the Ti/TiN layer and the first conducting layer; (m) removing the dielectric spacer and the etching stop layer; (n) forming a dielectric layer over exposed portions of the storage electrode; and (o) forming a second conducting layer as an opposite electrode over the dielectric layer.

Claim 12

A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate, comprising the steps of: (a) forming a transistor including a gate, a drain and a source over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region; (d) forming a Ti/TiN layer covering the sidewall and bottom of the contact opening, and extending over the insulating layer; (e) forming a tungsten plug in the contact opening; (f) forming a first conducting layer over the exposed Ti/TiN surface, and electrically connecting the tungsten plug; (g) successively forming an etching stop layer and a mask layer over the first conducting layer, wherein the etching stop layer and the first conducting layer consist of different materials; (h) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed; (i) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (j) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the Ti/TiN layer, for defining a capacitor region; (k) removing uncovered Ti/TiN layer and uncovered etching stop layer to expose the first conducting layer; (l) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode including the tungsten plug, the Ti/TiN layer and the first conducting layer; (m) removing the dielectric spacer and the etching stop layer; (n) forming a dielectric layer over exposed portions of the storage electrode; and (o) forming a second conducting layer as an opposite electrode over the dielectric layer.

Claim 18

A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate, comprising the steps of: (a) forming a transistor including a gate, a drain and a source over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region; (d) forming a first Ti/TiN layer covering the sidewall and bottom of the contact opening, and extending over the insulating layer; (e) forming a tungsten plug in the contact opening; (f) forming a second Ti/TiN layer covering the tungsten plug and the first Ti/TiN layer, wherein the second Ti/TiN layer has a thickness greater than that of the first Ti/TiN layer; (g) forming a first conducting layer over the exposed second Ti/TiN surface, and electrically connecting the tungsten plug; (h) successively forming an etching stop layer and a mask layer over the first conducting layer, wherein the etching stop layer and the first conducting layer consist of different materials; (i) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed; (j) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (k) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the Ti/TiN layer, for defining a capacitor region; (l) removing uncovered first and second Ti/TiN layers and the uncovered etching stop layer to expose the first conducting layer; (m) anisotropically etching the first conducting layer to the second Ti/TiN layer by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode including the tungsten plug, the first Ti/TiN layer, the second Ti/TiN layer and the first conducting layer; (n) removing the dielectric spacer and the etching stop layer; (o) forming a dielectric layer over the exposed portions of the storage electrode; and (p) forming a second conducting layer as an opposite electrode over the dielectric layer.

Claim 19

A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate, comprising the steps of: (a) forming a transistor including a gate, a drain and a source over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region; (d) forming a first Ti/TiN layer covering the sidewall and bottom of the contact opening, and extending over the insulating layer; (e) forming a tungsten plug in the contact opening; (f) forming a second Ti/TiN layer covering the tungsten plug and the first Ti/TiN layer, wherein the second Ti/TiN layer has a thickness greater than that of the first Ti/TiN layer; (g) forming a first conducting layer over the exposed second Ti/TiN surface, and electrically connecting the tungsten plug; (h) successively forming an etching stop layer and a mask layer over the first conducting layer, wherein the etching stop layer and the first conducting layer consist of different materials; (i) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed; (j) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (k) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the Ti/TiN layer, for defining a capacitor region; (l) removing uncovered first and second Ti/TiN layers and the uncovered etching stop layer to expose the first conducting layer; (m) anisotropically etching the first conducting layer to the second Ti/TiN layer by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode including the tungsten plug, the first Ti/TiN layer, the second Ti/TiN layer and the first conducting layer; (n) removing the dielectric spacer and the etching stop layer; (o) forming a dielectric layer over the exposed portions of the storage electrode; and (p) forming a second conducting layer as an opposite electrode over the dielectric layer.