Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory

Claim 1

A method for fabricating double-crown-shaped stacked capacitors on a semiconductor substrate having device areas, comprising the steps of: forming on said semiconductor substrate said device areas surrounded and electrically isolated from each other by field oxide areas; depositing a planar first insulating layer on said substrate; depositing a planar second insulating layer on said substrate; depositing a first polysilicon layer on said second insulating layer; depositing a third insulating layer on said first polysilicon layer; etching first openings in said third insulating layer to said first polysilicon layer aligned over said device areas; depositing a conformal fourth insulating layer and anisotropically etching back forming sidewall spacers in said first openings; etching in said first openings said first polysilicon layer; anisotropically plasma etching said second and first insulating layers exposed in said first openings to said device areas thereby forming second openings for node contacts, and concurrently etching said third insulating layer to said first polysilicon layer, said first polysilicon layer serving as an etch-stop layer elsewhere over said substrate; depositing a conformal second polysilicon layer over said sidewall spacers and in said second openings thereby forming capacitor node contacts; depositing a spin-on glass layer having a planar surface and etching back said spin-on glass layer thereby exposing portions of said second polysilicon layer on top portions of said sidewall spacers; etching back said exposed portions of said second polysilicon layer on said top portions of said sidewall spacers thereby exposing said sidewall spacers; selectively removing said spin-on glass layer; anisotropically etching back, thereby further removing said second and first polysilicon layers to form an array of electrically isolated capacitor bottom electrodes for said stacked capacitors; selectively removing said sidewall spacers; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing and patterning a third polysilicon layer thereby forming top electrodes and completing said double-crown-shaped stacked capacitors self-aligned to said capacitor node contacts.

Claim 2

A method for fabricating double-crown-shaped stacked capacitors on a semiconductor substrate having device areas, comprising the steps of: forming on said semiconductor substrate said device areas surrounded and electrically isolated from each other by field oxide areas; depositing a planar first insulating layer on said substrate; depositing a planar second insulating layer on said substrate; depositing a first polysilicon layer on said second insulating layer; depositing a third insulating layer on said first polysilicon layer; etching first openings in said third insulating layer to said first polysilicon layer aligned over said device areas; depositing a conformal fourth insulating layer and anisotropically etching back forming sidewall spacers in said first openings; etching in said first openings said first polysilicon layer; anisotropically plasma etching said second and first insulating layers exposed in said first openings to said device areas thereby forming second openings for node contacts, and concurrently etching said third insulating layer to said first polysilicon layer, said first polysilicon layer serving as an etch-stop layer elsewhere over said substrate; depositing a conformal second polysilicon layer over said sidewall spacers and in said second openings thereby forming capacitor node contacts; depositing a spin-on glass layer having a planar surface and etching back said spin-on glass layer thereby exposing portions of said second polysilicon layer on top portions of said sidewall spacers; etching back said exposed portions of said second polysilicon layer on said top portions of said sidewall spacers thereby exposing said sidewall spacers; selectively removing said spin-on glass layer; anisotropically etching back, thereby further removing said second and first polysilicon layers to form an array of electrically isolated capacitor bottom electrodes for said stacked capacitors; selectively removing said sidewall spacers; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing and patterning a third polysilicon layer thereby forming top electrodes and completing said double-crown-shaped stacked capacitors self-aligned to said capacitor node contacts.

Claim 13

A method for fabricating an array of dynamic random access memory cells having double-crown-shaped stacked capacitors on a semiconductor substrate comprising the steps of: forming on said semiconductor substrate device areas surrounded and electrically isolated from each other by field oxide areas; providing field effect transistors (FETs) in said device areas, each of said transistors having a gate electrode formed from a patterned first polycide layer, and having first and second source/drain contact areas in said device areas; depositing a planar first insulating layer on said substrate; photoresist masking and anisotropically etching contact openings to said first source/drain contact areas of each said FET, thereby forming bit line contact openings for bit lines; forming a second polycide layer on said substrate; patterning said second polycide layer thereby forming said bit lines to said first source/drain contact areas; depositing a planar second insulating layer over said bit lines and elsewhere on said substrate; depositing a first polysilicon layer on said second insulating layer; depositing a third insulating layer and said first polysilicon layer; etching first openings in said third insulating layer to said first polysilicon layer aligned over said second source/drain contact areas; depositing a conformal fourth insulating layer and anisotropically etching back forming sidewall spacers in said first openings thereby reducing a width of said first openings; etching said first polysilicon layer in said first openings; anisotropically plasma etching said second and first insulating layers exposed in said first openings to said second source/drain contact areas thereby forming second openings for node contacts, and concurrently etching said third insulating layer to said first polysilicon layer, said first polysilicon layer serving as an etch-stop layer over said bit lines and elsewhere over said substrate; depositing a conformal second polysilicon layer over said sidewall spacers and in said second openings; depositing a spin-on glass layer having a planar surface and etching back said spin-on glass layer thereby exposing portions of said second polysilicon layer on top portions of said sidewall spacers; etching back said second polysilicon layer on said top portions of said sidewall spacers thereby exposing said sidewall spacers; selectively removing said spin-on glass layer; depositing a hemispherical silicon grain (HSG) layer and anisotropically etching back, said etching back further removing said second and first polysilicon layers to form an array of electrically isolated capacitor bottom electrodes; selectively removing said sidewall spacers; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing and patterning a third polysilicon layer thereby forming top electrodes and completing said double-crown-shaped stacked capacitors.

Claim 14

A method for fabricating an array of dynamic random access memory cells having double-crown-shaped stacked capacitors on a semiconductor substrate comprising the steps of: forming on said semiconductor substrate device areas surrounded and electrically isolated from each other by field oxide areas; providing field effect transistors (FETs) in said device areas, each of said transistors having a gate electrode formed from a patterned first polycide layer, and having first and second source/drain contact areas in said device areas; depositing a planar first insulating layer on said substrate; photoresist masking and anisotropically etching contact openings to said first source/drain contact areas of each said FET, thereby forming bit line contact openings for bit lines; forming a second polycide layer on said substrate; patterning said second polycide layer thereby forming said bit lines to said first source/drain contact areas; depositing a planar second insulating layer over said bit lines and elsewhere on said substrate; depositing a first polysilicon layer on said second insulating layer; depositing a third insulating layer and said first polysilicon layer; etching first openings in said third insulating layer to said first polysilicon layer aligned over said second source/drain contact areas; depositing a conformal fourth insulating layer and anisotropically etching back forming sidewall spacers in said first openings thereby reducing a width of said first openings; etching said first polysilicon layer in said first openings; anisotropically plasma etching said second and first insulating layers exposed in said first openings to said second source/drain contact areas thereby forming second openings for node contacts, and concurrently etching said third insulating layer to said first polysilicon layer, said first polysilicon layer serving as an etch-stop layer over said bit lines and elsewhere over said substrate; depositing a conformal second polysilicon layer over said sidewall spacers and in said second openings; depositing a spin-on glass layer having a planar surface and etching back said spin-on glass layer thereby exposing portions of said second polysilicon layer on top portions of said sidewall spacers; etching back said second polysilicon layer on said top portions of said sidewall spacers thereby exposing said sidewall spacers; selectively removing said spin-on glass layer; depositing a hemispherical silicon grain (HSG) layer and anisotropically etching back, said etching back further removing said second and first polysilicon layers to form an array of electrically isolated capacitor bottom electrodes; selectively removing said sidewall spacers; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing and patterning a third polysilicon layer thereby forming top electrodes and completing said double-crown-shaped stacked capacitors.