Process for fabricating a stacked capacitor having an I-shaped cross-section in a dynamic random access memory array

Claim 1

A process for fabricating a DRAM array on a silicon substrate, said process comprising the steps of: creating a plurality of separately isolated active areas arranged in parallel rows and parallel columns; creating a gate dielectric layer on top of each active area; depositing a first conductive layer superjacent surface of said DRAM array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said work line passes over a inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer; creating a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; depositing a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; depositing a third dielectric layer superjacent said second conductive layer; masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-shaped topology; depositing a first oxide layer superjacent said array surface of said waveform-shaped topology; creating a second aligned buried contact location at each said storage node junction in each said active area; depositing a third conductive layer superjacent said array surface said waveform-shaped topology in response to existing topology, said third conductive layer making contact to said storage node junctions at said second buried contact locations; etching back said third conductive layer thereby forming a planarized of said third conductive layer; depositing a fourth dielectric layer superjacent said third conductive layer; masking and etching said fourth dielectric layer thereby forming dielectric patterns aligned directly over said digit lines; depositing a fifth dielectric layer superjacent said dielectric patterns and exposed third conductive layer; etching said fifth dielectric layer thereby forming dielectric spacers adjacent said dielectric patterns, said spacer etching re-exposing a portion of said third conductive layer; depositing a fourth conductive layer superjacent said dielectric patterns and said dielectric spacers, said fourth conductive layer attaching to surface of said re-exposed third conductive layer; masking and etching said fourth conductive layer, said etching exposing underlying dielectric; wet etching said exposed underlying dielectric thereby exposing said third conductive layer; etching said third conductive layer thereby creating individual conductive storage node plates having said I-shaped cross-section; depositing a cell dielectric layer adjacent said coextensive said storage node plate and adjacent said array surface; and depositing a fifth conductive layer adjacent and coextensive said cell dielectric layer to form a cell plate common to the entire memory array.