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US5986925A
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Magnetoresistive random access memory device providing simultaneous reading of two cells and operating method
Assignee: Everspin Technologies Inc
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Filing: 1998-04-07
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Granted: 1999-11-16
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Expires: 2018-04-07
Abstract
Abstract A magnetoresistive random access memory (MRAM) having a novel circuit configuration (40) is provided. The MRAM device includes a plurality of magnetic memory cells in a memory array (41). The magnetic memory cell includes magnetoresistive layers separated by an insulating layer which forms a tunneling junction between the magnetoresistive layers. A sense line selector (42, 43) selects two memory cells (48) in which a sense current (66) is applied from a current source (45). Voltages generated over the memory cells are sensed and compared to predetermined threshold voltages to provide outputs (OUT1, OUT2) which correspond to states stored in the pair of the memory cells (48). This new MRAM device attains non-volatile random access memory with high-speed and high-density.
Inventors
- 👤 Peter K. Naji
- 👤 Russell G. Byrd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5607; G11C11/02; G11C11/14; G11C11/15; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5615
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
76 words
A magnetic random access memory device comprising: a memory array including a plurality of memory cells, each of the memory cells having magnetoresistive layers separated by an insulating layer; a sense line selector for selecting two memory cells in the memory array; a current source for simultaneously providing a sense current to the two memory cells; and an output circuit for sensing two voltages to provide an output indicating states stored in the two memory cells.
Claim 2
Dependent Claim
76 words
A magnetic random access memory device comprising: a memory array including a plurality of memory cells, each of the memory cells having magnetoresistive layers separated by an insulating layer; a sense line selector for selecting two memory cells in the memory array; a current source for simultaneously providing a sense current to the two memory cells; and an output circuit for sensing two voltages to provide an output indicating states stored in the two memory cells.
Claim 3
Dependent Claim
34 words
The magnetic random access memory device as claimed in claim 1 wherein the memory array comprises a plurality of memory banks, each of the memory banks including a plurality of pairs of memory cells.
Claim 4
Dependent Claim
36 words
The magnetic random access memory device as claimed in claim 2 wherein each of the memory banks further includes a plurality of transistors, two of the transistors being coupled to the two memory cells in series.
Claim 5
Dependent Claim
64 words
The magnetic random access memory device as claimed in claim 1 wherein the memory selector comprises: a sense line selector for selecting first and second sense lines; and a word line selector for selecting a row of memory cells, so that the current source, the two memory cells and the first and second sense lines are coupled in series for providing the sense current.
Claim 6
Dependent Claim
34 words
The magnetic random access memory device as claimed in claim 4 wherein the sense line selector couples the first sense line to the current source and the second sense line to a common line.
Claim 7
Dependent Claim
75 words
The magnetic random access memory device as claimed in claim 1 wherein the output circuit comprises: a comparator for comparing first and second voltages to predetermined threshold voltages to provide digital signals, the first voltage being generated over one memory cell in the two memory cells and the second voltage being generated across both of the two memory cells; and an encoder for encoding the digital signals to encoded data according to a predetermined procedure.
Claim 8
Dependent Claim
86 words
The magnetic random access memory device as claimed in claim 1 wherein the output circuit comprises: a summation circuit for summing first and second voltages generated across the memory cells to produce a summation voltage, the first voltage being generated across one of the two memory cells and the second voltage being generated across both of the two memory cells; a converter for converting the summation voltage to digital signals; and an encoder for encoding the digital signals to encoded data according to a predetermined procedure.
Claim 9
Dependent Claim
22 words
The magnetic random access memory device as claimed in claim 1 wherein the memory cell forms a tunneling junction between magnetoresistive layers.
Claim 10
Dependent Claim
121 words
A magnetic random access memory device comprising: a memory array including a plurality of memory cells forming rows and columns, each of the memory cells having magnetoresistive layers separated by an insulating layer which forms a tunneling junction between the magnetoresistive layers; a word line selector for selecting a row of memory cells in the memory array; a current source for providing a sense current to two memory cells; a sense line selector for selecting two sense lines and coupling one end of the sense line to the current source and another end of the sense line to a common line; and an output circuit for sensing two voltages to provide an output indicating states stored in the two memory cells.
Claim 11
Dependent Claim
121 words
A magnetic random access memory device comprising: a memory array including a plurality of memory cells forming rows and columns, each of the memory cells having magnetoresistive layers separated by an insulating layer which forms a tunneling junction between the magnetoresistive layers; a word line selector for selecting a row of memory cells in the memory array; a current source for providing a sense current to two memory cells; a sense line selector for selecting two sense lines and coupling one end of the sense line to the current source and another end of the sense line to a common line; and an output circuit for sensing two voltages to provide an output indicating states stored in the two memory cells.
Claim 12
Dependent Claim
73 words
The magnetic random access memory device as claimed in claim 9 wherein the output circuit comprises: a comparator for comparing first and second voltages to predetermined threshold voltages to provide digital signals, the first voltage being generated across one of the two memory cells and the second voltage being generated across both of the two memory cells; and an encoder for encoding the digital signals to encoded data according to a predetermined procedure.
Claim 13
Dependent Claim
86 words
The magnetic random access memory device as claimed in claim 9 wherein the output circuit comprises: a summation circuit for summing first and second voltages generated across the memory cells to produce a summation voltage, the first voltage being generated across one of the two memory cells and the second voltage being generated across both of the two memory cells; a converter for converting the summation voltage to digital signals; and an encoder for encoding the digital signals to encoded data according to a predetermined procedure.
Claim 14
Independent Claim
86 words
A method of sensing states stored in two memory cells arranged in a memory array, each of the memory cells having magnetoresistive layers separated by an insulating layer which forms a tunneling junction between the magnetoresistive layers, the method comprising the steps of: selecting the two memory cells; providing a sense current from a current source to the two memory cells; and comparing voltages generated across the memory cells with predetermined threshold voltages to provide an output indicating states stored in the pair of memory cells.
Claim 15
Independent Claim
86 words
A method of sensing states stored in two memory cells arranged in a memory array, each of the memory cells having magnetoresistive layers separated by an insulating layer which forms a tunneling junction between the magnetoresistive layers, the method comprising the steps of: selecting the two memory cells; providing a sense current from a current source to the two memory cells; and comparing voltages generated across the memory cells with predetermined threshold voltages to provide an output indicating states stored in the pair of memory cells.
Claim 16
Dependent Claim
72 words
The method as claimed in claim 12 wherein the step of comparing voltages generated over the memory cells with predetermined threshold voltages comprising the steps of: comparing first and second voltages with predetermined threshold voltages to provide digital signals, the first voltage being generated across one of the two memory cells and the second voltage being generated across both of the two memory cells; and encoding the digital signals to encoded data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |