Method and apparatus for implementing a dynamic adiabatic logic family

Claim 2

A gate for use in a logic cascade, the gate comprising: a first evaluate network to generate an output signal; a first precharge network coupled to an output of the first evaluate network; a second evaluate network to generate an output complement signal; and a second precharge network coupled to an output of the second evaluate network, wherein the first and second evaluate networks are coupled to a common power rail which carries a power clock signal so as to provide an approximately constant capacitive load to a power clock signal generation circuit and wherein each of the first and second evaluate networks includes a principal MOSFET switch and a complementary MOSFET switch, the complementary MOSFET switch having a threshold voltage different from that of the principal MOSFET switch.

Claim 3

The gate of claim 1 wherein the first and second precharge networks are coupled to the power rail.

Claim 4

The gate of claim 1 wherein the first and second evaluate networks are each pull-up networks, and the first and second precharge networks are each pull-down networks.

Claim 5

The gate of claim 1 wherein the first and second evaluate networks are each pull-down networks, and the first and second precharge networks are each pull-up networks.

Claim 6

The gate of claim 1 wherein the complementary MOSFET switch has a zero-biased threshold voltage that is higher than that of the principal MOSFET switch.

Claim 7

A logic cascade comprising: a first power rail carrying a first power clock signal; a second power rail carrying a second power clock signal; a first gate comprising: first and second pull-up evaluate networks, each coupled to the first power rail, and respectively to generate a first output signal and a first output complement signal in response to a first input signal and a first input complement signal; and first and second pull-down precharge networks, each coupled to the first power rail, and coupled to an output of the first and the second pull-up evaluate network respectively; and a second gate comprising: third and fourth pull-down evaluate networks, each coupled to the second power rail, and respectively to generate a second output signal and a second output complement signal in response to the first output signal and the first output complement signal generated by the first gate; and third and fourth pull-up precharge networks, each coupled to the second power rail, and coupled to an output of the third and the fourth pull-down evaluate network respectively, wherein each of the evaluate network includes a principal MOSFET switch and a complementary MOSFET switch, the complementary MOSFET switch having a threshold voltage different from that of the principal MOSFET switch.

Claim 8

A logic cascade comprising: a first power rail carrying a first power clock signal; a second power rail carrying a second power clock signal; a first gate comprising: first and second pull-up evaluate networks, each coupled to the first power rail, and respectively to generate a first output signal and a first output complement signal in response to a first input signal and a first input complement signal; and first and second pull-down precharge networks, each coupled to the first power rail, and coupled to an output of the first and the second pull-up evaluate network respectively; and a second gate comprising: third and fourth pull-down evaluate networks, each coupled to the second power rail, and respectively to generate a second output signal and a second output complement signal in response to the first output signal and the first output complement signal generated by the first gate; and third and fourth pull-up precharge networks, each coupled to the second power rail, and coupled to an output of the third and the fourth pull-down evaluate network respectively, wherein each of the evaluate network includes a principal MOSFET switch and a complementary MOSFET switch, the complementary MOSFET switch having a threshold voltage different from that of the principal MOSFET switch.

Claim 9

The logic cascade of claim 6 wherein the first and second power clock signals respectively comprise first and second waveforms which are out-of-phase by a predetermined amount.

Claim 10

The logic cascade of claim 7 wherein the first and second waveforms are out-of-phase by 90 degrees.

Claim 11

The logic cascade of claim 6 further comprising: a third power rail carrying a third power clock signal; a fourth power rail carrying a fourth power clock signal; a third gate comprising: fifth and sixth pull-up evaluate networks, each coupled to the third power rail, and respectively to generate a third output signal and a third output complement signal in response to the second output signal and the second output complement signal generated by the second gate; and the third power rail, and respectively associated with the fifth and sixth pull-up evaluate networks; and a fourth gate comprising: seventh and eighth pull-down evaluate networks, each coupled to the fourth power rail, and respectively to generate a fourth output signal and a fourth output complement signal in response to the third output signal and the third output complement signal generated by the third gate; and seventh and eighth pull-up precharge networks, each coupled to the fourth power rail, and respectively associated with the seventh and eighth pull-down evaluate networks.

Claim 12

The logic cascade of claim 9 wherein the third and fourth power clock signals respectively comprise third and fourth waveforms which are out-of-phase by a predetermined amount.

Claim 13

The logic cascade of claim 10 wherein the third and fourth waveforms are out-of-phase by 90 degrees.

Claim 14

The logic cascade of claim 10 wherein the first power clock signal comprises a first waveform, and the first and third waveforms are out-of phase by 180 degrees.

Claim 15

The logic cascade of claim 10 wherein the second power clock signal comprises a second waveform, and the second and fourth waveforms are out-of-phase by 180 degrees.

Claim 16

A gate for use in a logic cascade, the gate comprising: a first evaluate network to generate an output signal; a first precharge network coupled to an output of the first evaluate network; a second evaluate network to generate an output complement signal; and a second precharge network coupled to an output of the second evaluate network, each of the first and second evaluate networks including a principal MOSFET switch and a complementary MOSFET switch, the complementary MOSFET switch having a threshold voltage different from that of the principal MOSFET switch.

Claim 17

A gate for use in a logic cascade, the gate comprising: a first evaluate network to generate an output signal; a first precharge network coupled to an output of the first evaluate network; a second evaluate network to generate an output complement signal; and a second precharge network coupled to an output of the second evaluate network, each of the first and second evaluate networks including a principal MOSFET switch and a complementary MOSFET switch, the complementary MOSFET switch having a threshold voltage different from that of the principal MOSFET switch.

Claim 18

The gate of claim 14 wherein, for each of the first and second evaluate networks, the complementary MOSFET switch has a zero-biased threshold voltage that is higher than that of the principal MOSFET switch.