Semiconductor integrated circuit apparatus having a plurality of well bias voltage supply circuits

Claim 2

A MOS semiconductor integrated circuit apparatus comprising: a semiconductor substrate; a first well region formed in the upper surface of the semiconductor substrate; a first MOS semiconductor circuit including MOSFET formed in the first well region; first bias voltage supply means for supplying a bias voltage to the first well region; a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region; a second MOS semiconductor circuit including MOSFET formed in the second well region; and second bias voltage supply means for supplying a bias voltage to the second well region, wherein at least one of the first and second bias voltage supply means includes capacitors, diodes, and an inverter, for reducing variations in the bias voltage.

Claim 3

A semiconductor integrated circuit apparatus according to claim 1, wherein the first circuit includes an interface circuit for inputting and outputting data to and from the apparatus.

Claim 4

A semiconductor integrated circuit apparatus according to claim 2, wherein the second circuit includes a data memorizing circuit, and the apparatus is a data memorizing apparatus.

Claim 5

A semiconductor integrated circuit apparatus according to claim 2, wherein the second circuit includes a logic circuit.

Claim 6

A semiconductor integrated circuit apparatus according to claim 2, wherein the second circuit includes an analog circuit.

Claim 7

A semiconductor integrated circuit apparatus according to claim 2, wherein the first and second well regions are p-type well regions, and the first and second bias voltage supply means generate and supply negative voltages.

Claim 8

A semiconductor integrated circuit apparatus according to claim 3, wherein the second bias voltage supply means supplies a voltage lower than the first bias voltage supply means.

Claim 9

A semiconductor integrated circuit apparatus according to claim 1, further comprising: a third well region formed in the upper surface of the semiconductor substrate such that it does not contact the first and second well regions; a third circuit formed in the third well region; and third bias voltage supply means for supplying a bias voltage to the third well region.

Claim 10

A semiconductor integrated circuit apparatus according to claim 8, wherein the third bias voltage supply means includes a plurality of means, consisting of capacitors, diodes, and an inverter, for reducing variations in the bias voltage.

Claim 11

A MOS semiconductor integrated circuit apparatus comprising: a semiconductor substrate; a first well region formed in the upper surface of the semiconductor substrate; a first MOS semiconductor circuit including MOSFET formed in the first well region and including a circuit for inputting and outputting data to and from the apparatus; first bias voltage supply means for supplying a bias voltage to the first well region; a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region; a second MOS semiconductor circuit including MOSFET formed in the second well region and including a data memorizing circuit; second bias voltage supply means for supplying the second well region with a bias voltage lower than that of the first bias voltage supply means; a third well region formed in the upper surface of the semiconductor substrate such that it does not contact the first and second well regions; a third MOS semiconductor circuit including MOSFET formed in the third well region; and third bias voltage supply means for supplying the third well region with a bias voltage substantially equal to that of the first bias voltage supply means, wherein at least one of the first, second and third bias voltage supply means includes capacitors, diodes, and an inverter, for reducing variations in the bias voltage.

Claim 12

A MOS semiconductor integrated circuit apparatus comprising: a semiconductor substrate; a first well region formed in the upper surface of the semiconductor substrate; a first MOS semiconductor circuit including MOSFET formed in the first well region and including a circuit for inputting and outputting data to and from the apparatus; first bias voltage supply means for supplying a bias voltage to the first well region; a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region; a second MOS semiconductor circuit including MOSFET formed in the second well region and including a data memorizing circuit; second bias voltage supply means for supplying the second well region with a bias voltage lower than that of the first bias voltage supply means; a third well region formed in the upper surface of the semiconductor substrate such that it does not contact the first and second well regions; a third MOS semiconductor circuit including MOSFET formed in the third well region; and third bias voltage supply means for supplying the third well region with a bias voltage substantially equal to that of the first bias voltage supply means, wherein at least one of the first, second and third bias voltage supply means includes capacitors, diodes, and an inverter, for reducing variations in the bias voltage.