US5985753A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to manufacture dual damascene using a phantom implant mask
Assignee: Advanced Micro Devices Inc
•
Filing: 1998-08-19
•
Granted: 1999-11-16
•
Expires: 2018-08-19
Abstract
Abstract Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.
Inventors
- 👤 Allen S. Yu
- 👤 Paul J. Steffan
- 👤 Thomas C. Scholer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:12
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/093; H10W20/095; H10P; H10P50/00; H10P50/73; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10W20/081; H10W20/084; H10W20/086; H10W20/088; H10W20/0884
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
298 words
A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming an etch stop layer on a surface of the first layer of interlayer dielectric; forming a first layer of photoresist on a surface of the etch stop layer; etching the first layer of photoresist down to the surface of the etch stop layer with an etch pattern having dimensions of a via structure to be formed in the first layer of interlayer dielectric, wherein a portion of the surface of the etch stop layer is exposed; implanting ions in the exposed portion of the surface of the etch stop layer forming a heavily doped region in the etch stop layer having dimensions of the via structure to be formed in the first layer of interlayer dielectric; removing the first layer of photoresist and forming a second layer of interlayer dielectric on the surface of the etch stop layer; forming a second layer of photoresist on a surface of the second layer of interlayer dielectric; etching the second layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a trench structure to be formed in the second layer of interlayer dielectric; selectively etching the second layer of interlayer dielectric down to the surface of the etch stop layer, wherein a trench structure is formed in the second layer of interlayer dielectric; selectively etching the etch stop layer down to the surface of the first layer of interlayer dielectric; and selectively etching the first layer of interlayer dielectric down to the surface of the semiconductor substrate, wherein the via structure is formed in the first layer of interlayer dielectric.
Claim 2
Independent Claim
298 words
A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming an etch stop layer on a surface of the first layer of interlayer dielectric; forming a first layer of photoresist on a surface of the etch stop layer; etching the first layer of photoresist down to the surface of the etch stop layer with an etch pattern having dimensions of a via structure to be formed in the first layer of interlayer dielectric, wherein a portion of the surface of the etch stop layer is exposed; implanting ions in the exposed portion of the surface of the etch stop layer forming a heavily doped region in the etch stop layer having dimensions of the via structure to be formed in the first layer of interlayer dielectric; removing the first layer of photoresist and forming a second layer of interlayer dielectric on the surface of the etch stop layer; forming a second layer of photoresist on a surface of the second layer of interlayer dielectric; etching the second layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a trench structure to be formed in the second layer of interlayer dielectric; selectively etching the second layer of interlayer dielectric down to the surface of the etch stop layer, wherein a trench structure is formed in the second layer of interlayer dielectric; selectively etching the etch stop layer down to the surface of the first layer of interlayer dielectric; and selectively etching the first layer of interlayer dielectric down to the surface of the semiconductor substrate, wherein the via structure is formed in the first layer of interlayer dielectric.
Claim 3
Dependent Claim
35 words
The method of claim 1 further comprising filling the via structure formed in the first layer of interlayer dielectric and the trench structure formed in the second layer of interlayer dielectric with a conductive material.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein the conductive material is selected from the group consisting of aluminum, tungsten and copper.
Claim 5
Dependent Claim
28 words
The method of claim 3 wherein the etch stop layer is formed from a material selected from the group consisting of SiON and Si 3 N 4 .
Claim 6
Dependent Claim
24 words
The method of claim 4 wherein the ions implanted in the etch stop layer are selected from the group consisting of arsenic and phosphorus.
Claim 7
Independent Claim
383 words
A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming an etch stop layer on a surface of the first layer of interlayer dielectric; forming a second layer of interlayer dielectric on a surface of the etch stop layer; forming a first layer of photoresist on a surface of the second layer of interlayer dielectric; etching the first layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a via structure to be formed in the first layer of interlayer dielectric, wherein a portion of the surface of the second layer of interlayer dielectric is exposed; implanting ions in the exposed portion of the second layer of interlayer dielectric forming a heavily doped region in the second layer of interlayer dielectric having dimensions of the via structure to be formed in the first layer of interlayer dielectric; removing the first layer of photoresist and forming a second layer of photoresist on the surface of the second layer of interlayer dielectric; etching the second layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a trench structure to be formed in the second layer of interlayer dielectric; selectively etching the second layer of interlayer dielectric wherein a portion of the second layer of interlayer dielectric is etched and the heavily doped region in the second layer of interlayer dielectric allows the second layer of interlayer dielectric to be etched down to the surface of the etch stop layer exposing a region of the etch stop layer having dimensions of the via structure to be formed in the first layer of interlayer dielectric; selectively etching the exposed region of the etch stop layer down to the surface of the first layer of interlayer dielectric exposing a region of the first layer of interlayer dielectric having dimensions of the via structure to be formed in the first layer of interlayer dielectric; selectively etching the exposed region of the first layer of interlayer dielectric down to the surface of the semiconductor substrate, wherein the via structure is formed in the first layer of interlayer dielectric.
Claim 8
Independent Claim
383 words
A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming an etch stop layer on a surface of the first layer of interlayer dielectric; forming a second layer of interlayer dielectric on a surface of the etch stop layer; forming a first layer of photoresist on a surface of the second layer of interlayer dielectric; etching the first layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a via structure to be formed in the first layer of interlayer dielectric, wherein a portion of the surface of the second layer of interlayer dielectric is exposed; implanting ions in the exposed portion of the second layer of interlayer dielectric forming a heavily doped region in the second layer of interlayer dielectric having dimensions of the via structure to be formed in the first layer of interlayer dielectric; removing the first layer of photoresist and forming a second layer of photoresist on the surface of the second layer of interlayer dielectric; etching the second layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a trench structure to be formed in the second layer of interlayer dielectric; selectively etching the second layer of interlayer dielectric wherein a portion of the second layer of interlayer dielectric is etched and the heavily doped region in the second layer of interlayer dielectric allows the second layer of interlayer dielectric to be etched down to the surface of the etch stop layer exposing a region of the etch stop layer having dimensions of the via structure to be formed in the first layer of interlayer dielectric; selectively etching the exposed region of the etch stop layer down to the surface of the first layer of interlayer dielectric exposing a region of the first layer of interlayer dielectric having dimensions of the via structure to be formed in the first layer of interlayer dielectric; selectively etching the exposed region of the first layer of interlayer dielectric down to the surface of the semiconductor substrate, wherein the via structure is formed in the first layer of interlayer dielectric.
Claim 9
Dependent Claim
35 words
The method of claim 5 further comprising filling the via structure formed in the first layer of interlayer dielectric and the trench structure formed in the second layer of interlayer dielectric with a conductive material.
Claim 10
Dependent Claim
20 words
The method of claim 6 wherein the conductive material is selected from the group consisting of aluminum, tungsten and copper.
Claim 11
Dependent Claim
28 words
The method of claim 7 wherein the etch stop layer is formed from a material selected from the group consisting of SiON and Si 3 N 4 .
Claim 12
Dependent Claim
24 words
The method of claim 8 wherein the ions implanted in the second layer of interlayer dielectric from the group consisting of arsenic and phosphorus.
References Cited (Backward Citations)
US4789648A
Cited
US5354711A
Cited
US5858877A
Cited
US5578523A
Cited
US5897369A
Cited
US5783485A
Cited
US5869395A
Cited
US5882996A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |