US5983307A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical circuit for exchanging data between a microprocessor and a memory and computer comprising a circuit of this type
Assignee: Bull SAS
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Filing: 1997-11-03
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Granted: 1999-11-09
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Expires: 2017-11-03
Abstract
Abstract In order to allow an external memory space to enter into the memory space of a microprocessor (43) comprising a cache memory (94), an integrated circuit (42) serves as an interface between the microprocessor (43) and a memory unit (8, 9, 12) constituting the external memory space. The integrated circuit (42) comprises a stack (91) sized for containing a data block from the memory unit (8, 9, 12) such that the block from the memory unit (8, 9, 12) is seen as one or more blocks in the cache memory (94), and a register (93) belonging to the memory space of the microprocessor (43) adapted to contain the coordinates for access to the memory unit (8, 9, 12).
Inventors
- 👤 Jack Abily
- 👤 Jean Yujun Qian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:45
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
137 words
An electrical circuit (5, 7, 41) comprising: a memory unit (8, 9, 12), a microprocessor (43) for exchanging data with the memory unit (8, 9, 12), said memory unit being disposed external to a memory space of the microprocessor, said microprocessor comprising a cache memory (94), and an integrated circuit (42) serving as an interface between the microprocessor (43) and the memory unit (8, 9, 12), the integrated circuit (42) comprising: a stack (91) adapted to contain a data block of the memory unit (8, 9, 12) such that the block from the memory unit (8, 9, 12) is seen as one or more blocks in the cache memory (94), and a register (92) belonging to the memory space of the microprocessor (43), and adapted to contain addresses for access to the memory unit (8, 9, 12).
Claim 2
Dependent Claim
137 words
An electrical circuit (5, 7, 41) comprising: a memory unit (8, 9, 12), a microprocessor (43) for exchanging data with the memory unit (8, 9, 12), said memory unit being disposed external to a memory space of the microprocessor, said microprocessor comprising a cache memory (94), and an integrated circuit (42) serving as an interface between the microprocessor (43) and the memory unit (8, 9, 12), the integrated circuit (42) comprising: a stack (91) adapted to contain a data block of the memory unit (8, 9, 12) such that the block from the memory unit (8, 9, 12) is seen as one or more blocks in the cache memory (94), and a register (92) belonging to the memory space of the microprocessor (43), and adapted to contain addresses for access to the memory unit (8, 9, 12).
Claim 3
Dependent Claim
43 words
The electrical circuit (5, 7, 41) according to claim 1, characterized in that addressing of the stack (91) in the memory space of the microprocessor encodes a physical block address and a mode for reading or writing said block in the stack (91).
Claim 4
Dependent Claim
50 words
The electrical circuit (5, 7, 41) according to claim 1, characterized in that addressing of the register (93) in the memory space of the microprocessor encodes its physical address and an input of a port (51, 54, 55) from the integrated circuit (42) to a storage unit (8, 9, 12).
Claim 5
Dependent Claim
31 words
The electrical circuit (5, 7, 41) according to claim 1, characterized in that said circuit is adapted to pass through data coded in nine bits to data encoded in eight bits.
Claim 6
Dependent Claim
125 words
A computer comprising an electrical circuit including a microprocessor (43) for exchanging data with a memory unit (8, 9, 12) external to a memory space of the microprocessor, said microprocessor comprising a cache memory (94), and an integrated circuit (42) serving as an interface between the microprocessor (43) and the memory unit (8, 9, 12), the integrated circuit (42) comprising: a stack (91) adapted to contain a data block of the memory unit (8, 9, 12) such that the block from the memory unit (8, 9, 12) is seen as one or more blocks in the cache memory (94), and a register (92) belonging to the memory space of the microprocessor (43), adapted to contain addresses for access to the memory unit (8, 9, 12).
Claim 7
Dependent Claim
125 words
A computer comprising an electrical circuit including a microprocessor (43) for exchanging data with a memory unit (8, 9, 12) external to a memory space of the microprocessor, said microprocessor comprising a cache memory (94), and an integrated circuit (42) serving as an interface between the microprocessor (43) and the memory unit (8, 9, 12), the integrated circuit (42) comprising: a stack (91) adapted to contain a data block of the memory unit (8, 9, 12) such that the block from the memory unit (8, 9, 12) is seen as one or more blocks in the cache memory (94), and a register (92) belonging to the memory space of the microprocessor (43), adapted to contain addresses for access to the memory unit (8, 9, 12).
Claim 8
Dependent Claim
39 words
A computer according to claim 5, characterized in that addressing of the stack (91) in the memory space of the microprocessor encodes a physical block address and a mode for reading or writing said block in the stack (91).
Claim 9
Dependent Claim
46 words
A computer according to claim 5, characterized in that addressing of the register (93) in the memory space of the microprocessor encodes its physical address and an input of a port (51, 54, 55) from the integrated circuit (42) to a storage unit (8, 9, 12).
Claim 10
Dependent Claim
27 words
A computer according to claim 5, characterized in that said circuit is adapted to pass through data encoded in nine bits to data coded in eight bits.
Claim 11
Dependent Claim
85 words
A process for obtaining in a cache memory (94) of a microprocessor (43) an image of a data block to be read or written in a memory space (8, 9, 12) external to that of the microprocessor (43), characterized in that said process comprises a step for loading said block in bursts from registers (91) having a first label (rwxmu9d) for reading said block and for storing said block in bursts in the same registers (91) having a second label (rwxmu8d) for writing said block.
Claim 12
Dependent Claim
85 words
A process for obtaining in a cache memory (94) of a microprocessor (43) an image of a data block to be read or written in a memory space (8, 9, 12) external to that of the microprocessor (43), characterized in that said process comprises a step for loading said block in bursts from registers (91) having a first label (rwxmu9d) for reading said block and for storing said block in bursts in the same registers (91) having a second label (rwxmu8d) for writing said block.
Claim 13
Dependent Claim
40 words
The process according to claim 9, characterized in that the first label (rwxmu9d) the register (91) encodes its loading into the microprocessor (43) in bytes compatible with a data path width accessible to registers (GPR0, GPR7) of the microprocessor (43).
Claim 14
Dependent Claim
47 words
The process according to claim 9, characterized in that the second label (rwxmu8d) the register (91) encodes its storage beginning with registers (GPR0, GPR15) of the microprocessor (43) in bytes compatible with a number of bits possessed by a set of bytes from the external memory space.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |