EP0437712A2
Expired / Lapsed
EP
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Tandem cache memory
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1990-11-30
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Granted: —
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Expires: 2010-11-30
Abstract
Abstract Tandem cache memory comprising a first cache for storing a plurality of instructions more recently requested by a processor and for providing them to the processor, following a new request, without need to fetch them from a working memory and a second cache for reading from the working memory and storing a plurality of prefetched instruction blocks having subsequent addresses in increasing order relative to a current instruction requested for execution by the processor and for providing any one of the prefetched instruction blocks to both the processor and the first cache on processor request, if the processor requests an instruction which is not in the first cache but is stored in the second cache.
Inventors
- 👤 Ferruccio Zulian
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859; G06F12/0893; G06F12/0897; G06F12/0862
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
343 words
Tandem cache memory comprising a first cache for storing information blocks and having an address input, an information input/output and a signal output for signaling with a signal HIT respectively asserted and desserted if an information referenced by an address received at said address input is stored in said first cache or not, said first cache outputing said referenced information at said information input/output on assertion of said HIT signal, a second cache for storing information blocks referenced by subsequent ordered addresses and having an address input and address output, an information input, an information output and an input for receiving said HIT signal from said first cache, said second cache comprising logical means, triggered by said signal HIT being deasserted, for cheching if an information referenced by an address received at said address input is stored in said second cache or not stored and, if such information is not stored, said logical means requesting to a working memory and loading in said second cache a plurality of information blocks having subsequent addresses of increasing order, the lesser of said subsequent addresses referencing a first block containing the information referenced by said address received at said address input, said logical means transferring said first block to said information output and instructing said first cache to store said first block, as soon as it is received from said working memory, without waiting to have entirely received said plurality of information blocks, and if such information is stored, said logical means enabling said information output to output an information block containing the information referenced by said address received at said address input and instructing said first cache to store said output information block, and said logical means further checking if the address referencing said output block differs from the higher of the addresses of the blocks stored in said second cache by less than a predetermined amount and in the affirmative requesting to said working memory and loading in said second cache a plurality of information blocks having ordered addresses next following said higher address.
Claim 2
Dependent Claim
170 words
Tandem cache memory as in claim 1, where said second cache comprises a plurality of registers, each for storing an information block, and said logical means comprises, a first register for storing the address of a block stored in said second cache having the lesser among the addresses of the blocks stored in said second cache, a second register for storing the address of a block next following the highlest of the addresses of the blocks stored in said second cache, and comparison means for checking if an address received at said address input is higher than or equal to the address stored in said first register and lesser than the address stored in said second register and in the affirmative said comparison means generating a signal (HIT1) asserted, said logical means, on the occurrence of said HIT1 signal asserted, enabling one in said plurality or registers to output an information block stored therein, said one register being selected by a field of the address received at said address input.
References Cited (Backward Citations)
No citation records indexed.
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