EP0398178A2
Expired / Lapsed
EP
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Data communication control device
Assignee: Toshiba Corp
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Filing: 1990-05-11
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Granted: —
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Expires: 2010-05-11
Abstract
Abstract A data communication control device is constructed to control data transmission between a network bus (NB) and a system bus (SB). The data communication control device includes a network bus interface (10) connected to the network bus (NB), a system bus interface (60) connected to the system bus (SB), an FIF o /RAM (90) including a two-port memory (70) for storing transmission data, a direct memory access (50) for executing access of the two-part memory (70) in the FIF o /RAM (90), a microprocessor (20) for controlling the network bus interface (10), system bus interface (60), FIF o /RAM (90), and direct memory access (50) on data transmission. A port 1 of the two-port memory (70) in the FIF o /RAM (90) is connected to the network bus interface (10), microprocessor (20), direct memory access (50) through a first bus (B₄). A port 2 of the two-port memory (70) in the FIF o /RAM (90) is connected to the direct memory access (50) through a second bus (B₅). The micorprocessor (20) is connected to the system bus interface (60) through a third bus (B₆). The direct memory access (50) is connected to the system bus interface (60) through a fourth bus (B₇).
Inventors
- 👤 Eiichi Katsumata
- 👤 Koichi Tanaka
- 👤 Toshiyuki Yaguchi
- 👤 Akira Kanuma
- 👤 Akihito Nishikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
160 words
A data communication control device for controlling data transmission between a network bus and a system bus, comprising: a network bus interface connected to the network bus; a system bus interface connected to the system bus; an FIF o /RAM including a two-port memory for storing transmission data; a direct memory access for executing access of the two-port memory in the FIF o /RAM; a microprocessor for controlling the network bus interface, system bus interface, FIF o /RAM, and direct memory access on data transmission; a first bus for connecting a port 1 of the two-port memory in the FIF o /RAM to the network bus interface, microprocessor, direct memory access; a second bus for connecting a port 2 of the two-port memory in the FIF o /RAM to the direct memory access; a third bus for connecting the microprocessor to the system bus interface; and a fourth bus for connecting the direct memory access to the system bus interface.
Claim 2
Dependent Claim
160 words
A data communication control device for controlling data transmission between a network bus and a system bus, comprising: a network bus interface connected to the network bus; a system bus interface connected to the system bus; an FIF o /RAM including a two-port memory for storing transmission data; a direct memory access for executing access of the two-port memory in the FIF o /RAM; a microprocessor for controlling the network bus interface, system bus interface, FIF o /RAM, and direct memory access on data transmission; a first bus for connecting a port 1 of the two-port memory in the FIF o /RAM to the network bus interface, microprocessor, direct memory access; a second bus for connecting a port 2 of the two-port memory in the FIF o /RAM to the direct memory access; a third bus for connecting the microprocessor to the system bus interface; and a fourth bus for connecting the direct memory access to the system bus interface.
Claim 3
Dependent Claim
136 words
The data communication control device as claimed in claim 1, wherein in a data transmission mode from the system bus to the network bus, a command of data transmission from the system bus is transmitted to the system bus interface and transmitted to the microprocessor through the third bus, transmission data from the system bus are transmitted to the system bus interface and given to the port 2 of the two-port memory through the fourth bus, direct memory access, and second bus, the two-port memory arranges the transmission data in accordance with control of the microprocessor which received the transmission command, then, the transmission data arranged are given from the port 1 to the network bus interface through the first bus, thereafter, the transmission data are transmitted from the network bus interface to the network bus.
Claim 4
Dependent Claim
126 words
The data communication control device as claimed in claim 2, wherein in a data reception mode from the network bus to the system bus, a command of data reception from the system bus is transmitted to the system bus interface and transmitted to the microprocessor through the third bus, reception data from the network bus are transmitted to the network bus interface, and given to the port 1 of the two-port memory through the first bus, the two-port memory arranges the reception data in accordance with control of the microprocessor having received the reception command, then the reception data arranged are transmitted from the port 2 of the two-port memory to the system bus through the second bus, direct memory access, fourth bus, system bus interface.
Claim 5
Dependent Claim
152 words
A data communication control device for controlling data transmission between a network bus and a system bus, comprising: a network bus interface connected to the network bus; a system bus interface connected to the system bus; an FIF o /RAM including a two-port memory for storing transmission data; a direct memory access for executing access of the two-port memory in the FIF o /RAM; a microprocessor for controlling the network bus interface, system bus interface, FIF o /RAM, and direct memory access on data transmission; a first bus for connecting a port 1 of the two-port memory in the FIF o /RAM to the network bus interface, microprocessor, direct memory access, and system bus interface; a second bus for connecting a port 2 of the two-port memory in the FIF o /RAM to the direct memory access; and a third bus for connecting the direct memory access to the system bus interface.
Claim 6
Dependent Claim
152 words
A data communication control device for controlling data transmission between a network bus and a system bus, comprising: a network bus interface connected to the network bus; a system bus interface connected to the system bus; an FIF o /RAM including a two-port memory for storing transmission data; a direct memory access for executing access of the two-port memory in the FIF o /RAM; a microprocessor for controlling the network bus interface, system bus interface, FIF o /RAM, and direct memory access on data transmission; a first bus for connecting a port 1 of the two-port memory in the FIF o /RAM to the network bus interface, microprocessor, direct memory access, and system bus interface; a second bus for connecting a port 2 of the two-port memory in the FIF o /RAM to the direct memory access; and a third bus for connecting the direct memory access to the system bus interface.
References Cited (Backward Citations)
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