Patent US5982786A successfully refreshed from Google Patents.
US5982786A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuits and methods for framing one or more data streams
Assignee: RPX Corp
•
Filing: 1997-11-21
•
Granted: 1999-11-09
•
Expires: 2017-11-21
Abstract
Abstract A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.
Inventors
- 👤 Edward L. Grivna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:39
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/434; H04N21/4342; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608; H04N21/20; H04N21/23; H04N21/236; H04N21/23602; H04L; H04L7/00; H04L7/04; H04L7/08
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
136 words
A circuit for framing an input data stream to a periodic signal, comprising: a register circuit comprising a plurality of registers configured to store information and to present a first output and a second output in response to (i) said input data stream and (ii) said periodic signal; a logic circuit comprising a first comparator circuit configured to present a first output signal in response to a comparison between (i) the information stored in a second and third one of said plurality of registers and (ii) information stored in a first offset register, said logic circuit configured to (i) detect a predetermined bit sequence and (ii) present a control signal; and a multiplexor circuit configured to present one or more multiplexed signals comprising said first output and said second output in response to said control signal.
Claim 2
Dependent Claim
136 words
A circuit for framing an input data stream to a periodic signal, comprising: a register circuit comprising a plurality of registers configured to store information and to present a first output and a second output in response to (i) said input data stream and (ii) said periodic signal; a logic circuit comprising a first comparator circuit configured to present a first output signal in response to a comparison between (i) the information stored in a second and third one of said plurality of registers and (ii) information stored in a first offset register, said logic circuit configured to (i) detect a predetermined bit sequence and (ii) present a control signal; and a multiplexor circuit configured to present one or more multiplexed signals comprising said first output and said second output in response to said control signal.
Claim 3
Dependent Claim
31 words
The circuit according to claim 1, wherein the information stored in said first offset register is generated in response to information stored in a first one of said plurality of registers.
Claim 4
Dependent Claim
46 words
The circuit according to claim 2, wherein said logic circuit further comprises: a second comparator circuit configured to present a second output signal in response to a comparison between (i) the information stored in said second register and (ii) information stored in a second offset register.
Claim 5
Dependent Claim
35 words
The circuit according to claim 3, wherein the information stored in said second offset register is generated in response to (i) the information stored in said first offset register and (ii) the first output signal.
Claim 6
Dependent Claim
50 words
The circuit according to claim 3, wherein said logic circuit further comprises: a third offset register configured to store information in response to (i) the information stored in said second offset register, (ii) a feedback of the information stored in the third offset register and (iii) the second output signal.
Claim 7
Dependent Claim
29 words
The circuit according to claim 5, wherein said third offset register is configured to generate said control signal in response to the information stored in said third offset register.
Claim 8
Dependent Claim
17 words
The circuit according to claim 1, wherein said predetermined bits sequence comprises a timing reference symbol (TRS).
Claim 9
Dependent Claim
14 words
The circuit according to claim 1, wherein said multiplexed signal comprises a multi-bit signal.
Claim 10
Dependent Claim
23 words
The circuit according to claim 8, wherein said first output and said second output of said register circuit each comprise a multi-bit signal.
Claim 11
Dependent Claim
31 words
The circuit according to claim 9, wherein said multiplexor circuit comprises a plurality of multiplexors each configured to present a bit of said multiplexed signal in response to said control signal.
Claim 12
Dependent Claim
25 words
The circuit according to claim 1, wherein said logic circuit further comprises an encoder circuit configured to present the information to said first offset register.
Claim 13
Dependent Claim
144 words
A circuit for framing an input data stream to a timing signal, comprising: an input register comprising a plurality of registers configured to present an output in response to (i) said input data stream and (ii) said timing signal; a logic circuit comprising a first comparator circuit configured to present a first output signal in response to a comparison between (i) the information stored in a second and third one of said plurality of registers and (ii) information stored in a first offset register, said logic circuit configured to (i) detect a predetermined bit sequence and (ii) present a control signal; a multiplexor circuit configured to present a multiplexed signal in response to (i) said input data stream and (ii) said control signal; and an output register configured to present one or more output signals in response to said one or more multiplexed signals.
Claim 14
Dependent Claim
144 words
A circuit for framing an input data stream to a timing signal, comprising: an input register comprising a plurality of registers configured to present an output in response to (i) said input data stream and (ii) said timing signal; a logic circuit comprising a first comparator circuit configured to present a first output signal in response to a comparison between (i) the information stored in a second and third one of said plurality of registers and (ii) information stored in a first offset register, said logic circuit configured to (i) detect a predetermined bit sequence and (ii) present a control signal; a multiplexor circuit configured to present a multiplexed signal in response to (i) said input data stream and (ii) said control signal; and an output register configured to present one or more output signals in response to said one or more multiplexed signals.
Claim 15
Dependent Claim
15 words
The circuit according to claim 12, wherein said timing signal comprises a bit clock signal.
Claim 16
Dependent Claim
26 words
The circuit according to claim 12, wherein said a control signal is generated in response to (i) said timing signal and (ii) said input data stream.
Claim 17
Dependent Claim
14 words
The circuit according to claim 12, wherein said multiplexed signal comprises a multi-bit signal.
Claim 18
Dependent Claim
22 words
The circuit according to claim 15, wherein said input register circuit stores and presents a plurality of bits as a multi-bit signal.
Claim 19
Dependent Claim
24 words
The circuit according to claim 16, wherein said multiplexor circuit comprises a plurality of multiplexors each configured to present one of said multiplexed signals.
Claim 20
Dependent Claim
17 words
The circuit according to claim 12, wherein said predetermined bit sequence comprises a timing reference symbol (TRS).
References Cited (Backward Citations)
US5175767A
Cited
US5367544A
Cited
US5010559A
Cited
US5598424A
Cited
US5608734A
Cited
US5666547A
Cited
US5778000A
Cited
US5661763A
Cited
US5790607A
Cited
US5671223A
Cited
US5694056A
Cited
US5838631A
Cited
US5854794A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |