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US5598424A Expired / Lapsed US ⏱️ 0.0 years remaining

Error detection structure and method for serial or parallel data stream using partial polynomial check

Assignee: Xilinx Inc
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Filing: 1994-06-14
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Granted: 1997-01-28
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Expires: 2014-06-14
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Abstract

Abstract The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session. Both serial and parallel data streams may be checked.

Inventors

  • 👤 Charles R. Erickson
  • 👤 Philip M. Freidin
  • 👤 William A. Wilkie

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 03:50
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 119 words
Structure for detecting an error in a parallel set of bit streams, comprising: means for receiving said parallel set of bit streams; means for generating an error checkword from said parallel set of bit streams, at least one bit of said error checkword being a function of all previously transmitted bits in said parallel set of bit streams; means for testing a function of said error checkword including said at least one bit; and means for counting bits in said parallel set of bit streams wherein at a given count said means for counting bits activates said means for testing a function; in which said means for generating an error checkword comprises a computer controlled by a software algorithm.
Claim 2
Dependent Claim 119 words
Structure for detecting an error in a parallel set of bit streams, comprising: means for receiving said parallel set of bit streams; means for generating an error checkword from said parallel set of bit streams, at least one bit of said error checkword being a function of all previously transmitted bits in said parallel set of bit streams; means for testing a function of said error checkword including said at least one bit; and means for counting bits in said parallel set of bit streams wherein at a given count said means for counting bits activates said means for testing a function; in which said means for generating an error checkword comprises a computer controlled by a software algorithm.
Claim 3
Dependent Claim 115 words
Structure for detecting an error in a parallel set of bit streams, comprising: means for receiving said parallel set of bit streams; means for generating an error checkword from said parallel set of bit streams, at least one bit of said error checkword being a function of all previously transmitted bits in said parallel set of bit streams; means for testing a function of said error checkword including said at least one bit; and means for counting bits in said parallel set of bit streams wherein at a given count said means for counting bits activates said means for testing a function; in which said means for generating an error checkword comprises a hardware circuit.
Claim 4
Dependent Claim 115 words
Structure for detecting an error in a parallel set of bit streams, comprising: means for receiving said parallel set of bit streams; means for generating an error checkword from said parallel set of bit streams, at least one bit of said error checkword being a function of all previously transmitted bits in said parallel set of bit streams; means for testing a function of said error checkword including said at least one bit; and means for counting bits in said parallel set of bit streams wherein at a given count said means for counting bits activates said means for testing a function; in which said means for generating an error checkword comprises a hardware circuit.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-01-28 2000-07-29 2001-01-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-01-28 2004-07-29 2005-01-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-01-28 2008-07-29 2009-01-28 $7700.00 Window Closed / Lapsed

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