Patent US5981331A successfully refreshed from Google Patents.
US5981331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor memory device with a high dielectric constant capacitor
Assignee: Renesas Electronics Corp
•
Filing: 1997-07-25
•
Granted: 1999-11-09
•
Expires: 2017-07-25
Abstract
Abstract In a semiconductor memory device and a manufacturing method thereof, a barrier metal layer having a step h 2 which is smaller than the step h 1 at the upper end of a contact hole is formed on the surface opposite to the contact hole. The barrier metal layer has a nitrogen concentration gradient which becomes higher from its lower layer to its upper layer. A semiconductor memory device provided with a highly planer capacitor lower electrode, and a method of manufacturing the semiconductor memory device can thus be provided.
Inventors
- 👤 Yoshikazu Tsunemine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10W20/046; Y; Y10; Y10S; Y10S257/00; Y10S257/906
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
A method of manufacturing a semiconductor memory device, comprising: forming an impurity region at a major surface of a semiconductor substrate; forming a plug electrode electrically connected to said impurity region in said contact hole down to a distance h 1 below an upper end of said contact hole; forming a metal layer on surfaces of said plug electrode and said interlayer insulating film; forming a barrier metal layer by annealing said metal layer in gas ambient including nitrogen atoms, said barrier metal layer having a step portion h 2 less than h 1 , on a surface opposite said contact hole, and said barrier metal layer having a film thickness of one-third to three times h 1 , said barrier metal layer formed of a material having a volume greater than that of the metal layer by expanding the volume of the metal layer during annealing; forming a capacitor lower electrode layer on the surface of said barrier metal layer; patterning said barrier metal layer and said capacitor lower electrode layer to a shape; forming a capacitor dielectric film of material having high dielectric constant to cover said capacitor lower electrode layer and said barrier metal layer; and forming a capacitor upper electrode to cover said capacitor dielectric film.
Claim 2
Independent Claim
210 words
A method of manufacturing a semiconductor memory device, comprising: forming an impurity region at a major surface of a semiconductor substrate; forming a plug electrode electrically connected to said impurity region in said contact hole down to a distance h 1 below an upper end of said contact hole; forming a metal layer on surfaces of said plug electrode and said interlayer insulating film; forming a barrier metal layer by annealing said metal layer in gas ambient including nitrogen atoms, said barrier metal layer having a step portion h 2 less than h 1 , on a surface opposite said contact hole, and said barrier metal layer having a film thickness of one-third to three times h 1 , said barrier metal layer formed of a material having a volume greater than that of the metal layer by expanding the volume of the metal layer during annealing; forming a capacitor lower electrode layer on the surface of said barrier metal layer; patterning said barrier metal layer and said capacitor lower electrode layer to a shape; forming a capacitor dielectric film of material having high dielectric constant to cover said capacitor lower electrode layer and said barrier metal layer; and forming a capacitor upper electrode to cover said capacitor dielectric film.
Claim 3
Dependent Claim
33 words
The method of manufacturing a semiconductor memory device according to claim 1, wherein said gas ambient including nitrogen atoms is at least one selected from the group consisting of nitrogen, hydrazide and ammonia.
Claim 4
Dependent Claim
31 words
The method of manufacturing a semiconductor memory device according to claim 1, wherein said annealing is conducted for 15 seconds to 2 minutes at a temperature of 700 to 900° C.
Claim 5
Independent Claim
199 words
A method of manufacturing a semiconductor memory device comprising: forming an impurity region at a major surface of a semiconductor substrate; forming an interlayer insulating film having a contact hole connected to said impurity region on said major surface of said semiconductor substrate; forming a plug electrode electrically connected to said impurity region including silicon in said contact hole down to a distance h 1 below an upper end of said contact hole; forming a metal layer on surfaces of said plug electrode and said interlayer insulating film; forming a metal silicide layer between said plug electrode and said metal layer by a first annealing; annealing said metal suicide layer in a gas ambient including nitrogen atoms to form a nitride barrier metal layer having a film thickness of one-third to three times h 1 ; leaving said nitride barrier metal layer in the contact hole; forming a capacitor lower electrode on a surface of said nitride barrier metal layer and said insulating film; forming a capacitor dielectric film of material having a high dielectric constant to cover said capacitor lower electrode and said interlayer insulating film; and forming a capacitor upper electrode to cover said capacitor dielectric film.
Claim 6
Independent Claim
199 words
A method of manufacturing a semiconductor memory device comprising: forming an impurity region at a major surface of a semiconductor substrate; forming an interlayer insulating film having a contact hole connected to said impurity region on said major surface of said semiconductor substrate; forming a plug electrode electrically connected to said impurity region including silicon in said contact hole down to a distance h 1 below an upper end of said contact hole; forming a metal layer on surfaces of said plug electrode and said interlayer insulating film; forming a metal silicide layer between said plug electrode and said metal layer by a first annealing; annealing said metal suicide layer in a gas ambient including nitrogen atoms to form a nitride barrier metal layer having a film thickness of one-third to three times h 1 ; leaving said nitride barrier metal layer in the contact hole; forming a capacitor lower electrode on a surface of said nitride barrier metal layer and said insulating film; forming a capacitor dielectric film of material having a high dielectric constant to cover said capacitor lower electrode and said interlayer insulating film; and forming a capacitor upper electrode to cover said capacitor dielectric film.
Claim 7
Dependent Claim
33 words
The method of manufacturing a semiconductor memory device according to claim 4, wherein said gas ambient including nitrogen atoms is at least one selected from the group consisting of nitrogen, hydrazide and ammonia.
Claim 8
Dependent Claim
32 words
The method of manufacturing a semiconductor memory device according to claim 4, wherein said first annealing is conducted for 15 seconds to 2 minutes at a temperature of 700 to 900° C.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |