US5699291A
Expired / Lapsed
US
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Semiconductor memory device and manufacturing method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1996-08-01
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Granted: 1997-12-16
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Expires: 2016-08-01
Abstract
Abstract In a semiconductor memory device and a manufacturing method thereof, a barrier metal layer having a step h 2 which is smaller than the step h 1 at the upper end of a contact hole is formed on the surface opposite to the contact hole. The barrier metal layer has a nitrogen concentration gradient which becomes higher from its lower layer to its upper layer. A semiconductor memory device provided with a highly planer capacitor lower electrode, and a method of manufacturing the semiconductor memory device can thus be provided.
Inventors
- 👤 Yoshikazu Tsunemine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:01
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10W20/046; Y; Y10; Y10S; Y10S257/00; Y10S257/906
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
159 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed at said major surface of said semiconductor substrate; an interlayer insulating film formed at said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole down to a point h 1 below the upper end of said contact hole; a barrier metal layer covering surfaces of said plug electrode and said interlayer insulating film and having a step portion h 2 smaller than said h 1 on the surface opposite to said contact hole; a capacitor lower electrode formed only on the surface of said barrier metal layer; a capacitor dielectric film of material having high dielectric constant formed to cover said capacitor lower electrode and said barrier metal layer; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 2
Dependent Claim
159 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed at said major surface of said semiconductor substrate; an interlayer insulating film formed at said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole down to a point h 1 below the upper end of said contact hole; a barrier metal layer covering surfaces of said plug electrode and said interlayer insulating film and having a step portion h 2 smaller than said h 1 on the surface opposite to said contact hole; a capacitor lower electrode formed only on the surface of said barrier metal layer; a capacitor dielectric film of material having high dielectric constant formed to cover said capacitor lower electrode and said barrier metal layer; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 3
Dependent Claim
28 words
The semiconductor memory device according to claim 1, wherein said h 1 is 500 Å to 800 Å, and said h 2 is 100 Å to 200 Å.
Claim 4
Dependent Claim
18 words
The semiconductor memory device according to claim 1, wherein said barrier metal layer is nitride of refractory metal.
Claim 5
Dependent Claim
19 words
The semiconductor memory device according to claim 1, wherein said barrier metal layer is nitride of refractory metal silicide.
Claim 6
Dependent Claim
161 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed at said major surface of said semiconductor substrate; an interlayer insulating film formed on said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole; a barrier metal layer of metal nitride covering surfaces of said plug electrode and said interlayer insulating film, said barrier metal layer comprising a lower layer portion, and an upper layer portion, and having a concentration gradient of nitrogen which increases from said lower layer portion to said upper layer portion; a capacitor lower electrode formed only on the surface of said barrier metal layer; a capacitor dielectric film of material having high dielectric constant formed to cover said capacitor lower electrode and said barrier metal layer; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 7
Dependent Claim
161 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed at said major surface of said semiconductor substrate; an interlayer insulating film formed on said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole; a barrier metal layer of metal nitride covering surfaces of said plug electrode and said interlayer insulating film, said barrier metal layer comprising a lower layer portion, and an upper layer portion, and having a concentration gradient of nitrogen which increases from said lower layer portion to said upper layer portion; a capacitor lower electrode formed only on the surface of said barrier metal layer; a capacitor dielectric film of material having high dielectric constant formed to cover said capacitor lower electrode and said barrier metal layer; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 8
Dependent Claim
24 words
The semiconductor memory device according to claim 5, wherein said barrier metal layer is nitride of refractory metal or nitride of refractory metal silicide.
Claim 9
Dependent Claim
161 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed on said major surface of said semiconductor substrate; an interlayer insulating film formed at said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole down to a point h 1 below the upper end of said contact hole; a barrier metal layer formed on the surface of said plug electrode in said contact hole; a capacitor lower electrode covering surfaces of said barrier metal layer and said interlayer insulating film, and having a step portion h 2 smaller than said h 1 on the surface opposite to said contact hole; a capacitor dielectric film formed of material having high dielectric constant to cover said capacitor electrode and said interlayer insulating film; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 10
Dependent Claim
161 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed on said major surface of said semiconductor substrate; an interlayer insulating film formed at said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole down to a point h 1 below the upper end of said contact hole; a barrier metal layer formed on the surface of said plug electrode in said contact hole; a capacitor lower electrode covering surfaces of said barrier metal layer and said interlayer insulating film, and having a step portion h 2 smaller than said h 1 on the surface opposite to said contact hole; a capacitor dielectric film formed of material having high dielectric constant to cover said capacitor electrode and said interlayer insulating film; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 11
Dependent Claim
28 words
The semiconductor memory device according to claim 7, wherein said h 1 is 500 Å to 800 Å, and said h 2 is 100 Å to 200 Å.
Claim 12
Dependent Claim
18 words
The semiconductor memory device according to claim 7, wherein said barrier metal layer is nitride of refractory metal.
Claim 13
Dependent Claim
19 words
The semiconductor memory device according to claim 7, wherein said barrier metal layer is nitride of refractory metal silicide.
Claim 14
Dependent Claim
165 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed at said major surface of said semiconductor substrate; an interlayer insulating film formed on said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole; a barrier metal layer of metal nitride formed in said contact hole on the surface of said plug electrode., said barrier metal layer comprising a lower layer portion and an upper layer portion, and having a concentration gradient of nitrogen which increases from said lower layer portion to said upper layer portion; a capacitor lower electrode formed on surfaces of said barrier metal layer and said interlayer insulating film; a capacitor dielectric film of material having high dielectric constant formed to cover said capacitor lower electrode and said interlayer insulating film; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 15
Dependent Claim
165 words
A semiconductor memory device, comprising: a semiconductor substrate having a major surface; an impurity region formed at said major surface of said semiconductor substrate; an interlayer insulating film formed on said major surface of said semiconductor substrate and having a contact hole connected to said impurity region; a plug electrode electrically connected to said impurity region, and formed in said contact hole; a barrier metal layer of metal nitride formed in said contact hole on the surface of said plug electrode., said barrier metal layer comprising a lower layer portion and an upper layer portion, and having a concentration gradient of nitrogen which increases from said lower layer portion to said upper layer portion; a capacitor lower electrode formed on surfaces of said barrier metal layer and said interlayer insulating film; a capacitor dielectric film of material having high dielectric constant formed to cover said capacitor lower electrode and said interlayer insulating film; and a capacitor upper electrode formed to cover said capacitor dielectric film.
Claim 16
Dependent Claim
24 words
The semiconductor memory device according to claim 11, wherein said barrier metal layer is nitride of refractory metal or nitride of refractory metal silicide.
References Cited (Backward Citations)
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