Memory for operating synchronously with clock signals generated internally responsive to externally received control signals while outputting the clock signals via an external terminal

Claim 1

A memory device formed on one semiconductor substrate, the memory device comprising: address input terminals which are supplied with address signals; data input/output terminals for inputting/outputting data signals; control terminals which are supplied with control signals; a memory cell array having a plurality of memory cells arranged in a matrix format, the memory cells storing the data signals; an address decoder for selecting memory cells of the memory cell array by decoding the address signals; an internal timing generator which outputs a trigger signal in response to the control signals, the internal timing generator being coupled to the control terminals; a cycle timing generator including a self-excited oscillator which generates a clock signal in response to the trigger signal; and, an external terminal for outputting the clock signal while the data signals are inputted/outputted through the data input/output terminals, such that the memory device performs an internal operation in synchronism with the clock signal.