Method and apparatus for high bandwidth shared memory

Claim 2

Apparatus for providing high speed data communications with a shared memory having a random access port and a sequential access port, said shared memory communicating with a first processing control unit and at least one auxiliary processing device, the processing control unit requiring random access of said memory, said apparatus comprising; means for operatively connecting the processing control unit to the random access port of said shared memory, means for operatively connecting each auxiliary processing device to the sequential access port of said shared memory, and means connected between said shared memory and each of said auxiliary processing devices as well as said processing control unit, for controlling access to said shared memory by said processing control unit and each said auxiliary processing device for effecting high speed communications at both said random access and said serial access ports.

Claim 3

The apparatus of claim 1 further comprising means for connecting a data bus path between said processing control unit and said auxiliary processing devices, means for connecting, along respective address buses, said processing control unit and said plurality of auxiliary processing devices to said control means for providing said control means with addresses for use in data transfers, and means for connecting said controlling means to said shared memory along a common address bus.

Claim 4

The apparatus of claim 2 wherein said controlling means further comprises an address path and direct memory access control circuitry responsive to said address data for generating a data address for transmission to said memory over said common address path, and an arbitration control circuitry responsive to arbitration signals available from each of said processing control unit and said plurality of auxiliary processing devices for selecting one of said unit and devices for transferring data to or receiving data from said shared memory.

Claim 5

The apparatus of claim 1 wherein said means for controlling access to said shared memory further comprises means for determining priority of access to said memory by said processing control unit and said plurality of auxiliary devices.

Claim 6

The apparatus of claim 1 wherein said shared memory is a video random access memory.

Claim 7

The apparatus of claim 1 further comprising a data bus path connected between the processing control unit and said auxiliary processing devices.

Claim 8

Apparatus for sharing data in a remote processing system with a local processing system, each processing system having a central processing unit and at least one auxiliary processing device, said apparatus comprising means for operatively connecting each of said central processing units to a respective data bus, means for connecting each said data bus to a random access port of a respective shared memory having a random access port and a sequential access port, means for connecting each said auxiliary processing device to a respective sequential data bus, means for connecting each said sequential data bus to a sequential access port of said respective shared memory, means for selectively interconnecting said respective sequential data buses, a local system memory control means for receiving address and priority request data from said local system central processing unit and for generating a remote address control data for the remote system shared memory, and remote memory control means responsive to said remote address control data and a remote request from said local central processing unit for activating said interconnecting means for allowing bidirectional data transfer between said local and remote processor systems, including writing data in and reading data from said remote shared memory by an auxiliary device of the local processor system.

Claim 9

Apparatus for sharing data in a remote processing system with a local processing system, each processing system having a central processing unit and at least one auxiliary processing device, said apparatus comprising means for operatively connecting each of said central processing units to a respective data bus, means for connecting each said data bus to a random access port of a respective shared memory having a random access port and a sequential access port, means for connecting each said auxiliary processing device to a respective sequential data bus, means for connecting each said sequential data bus to a sequential access port of said respective shared memory, means for selectively interconnecting said respective sequential data buses, a local system memory control means for receiving address and priority request data from said local system central processing unit and for generating a remote address control data for the remote system shared memory, and remote memory control means responsive to said remote address control data and a remote request from said local central processing unit for activating said interconnecting means for allowing bidirectional data transfer between said local and remote processor systems, including writing data in and reading data from said remote shared memory by an auxiliary device of the local processor system.

Claim 12

The method of claim 8 further comprising the steps of prioritizing attempts to access said memory so that the access at said random access port takes highest priority.

Claim 13

The method of claim 8 wherein said controlling step comprises the steps of providing a common address path to said memory for addressing a first word of a memory transfer, and providing the memory with a block length when said address corresponds to a burst mode transfer of operation from one of said auxiliary processing devices.

Claim 14

The method of claim 8 further comprising the steps of connecting at least a second processing control unit to a random access port of a second shared memory, connecting at least a second auxiliary device to a sequential access port of said second shared memory, and controlling access to said shared memory connected to said first processing control unit by auxiliary devices connected to said second shared memory.