US5976926A
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Static memory cell and method of manufacturing a static memory cell
Assignee: Micron Technology Inc
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Filing: 1997-10-10
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Granted: 1999-11-02
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Expires: 2017-10-10
Abstract
Abstract A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.
Inventors
- 👤 Jeff Zhiqiang Wu
- 👤 Joseph Karniewicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:51
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/36; B; B82; B82Y; B82Y10/00; G11C11/56; G11C11/5621; H; H10; H10B; H10B10/00; H10D; H10D12/00; H10D12/411; G11C11/40; G11C11/41; G11C11/412; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
142 words
A semiconductor processing method of manufacturing a static memory cell, the method comprising: providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1×10 16 ions/cm 3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the drain having a third average n-type dopant concentration of at least 1×10 19 ions/cm 3 , and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming layers relative to the source to define, in combination with the source, a resonant tunnel diode.
Claim 2
Dependent Claim
142 words
A semiconductor processing method of manufacturing a static memory cell, the method comprising: providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1×10 16 ions/cm 3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the drain having a third average n-type dopant concentration of at least 1×10 19 ions/cm 3 , and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming layers relative to the source to define, in combination with the source, a resonant tunnel diode.
Claim 3
Dependent Claim
21 words
A semiconductor processing method in accordance with claim 1 wherein the layers formed relative the source are formed on the source.
Claim 4
Dependent Claim
25 words
A semiconductor processing method in accordance with claim 1 wherein the layers formed relative the source comprise alternating layers of conductive material and insulative material.
Claim 5
Dependent Claim
26 words
A semiconductor processing method in accordance with claim 1 wherein the layers formed relative the source comprise stacked alternating layers of conductive material and insulative material.
Claim 6
Dependent Claim
53 words
A semiconductor processing method in accordance with claim 1 wherein the layers formed relative the source comprise alternating layers of silicon and silicon oxide stacked on the source, including two layers of silicon and two layers of silicon oxide, one of the layers of silicon oxide being in junction relation to the source.
Claim 7
Independent Claim
209 words
A method of manufacturing and operating a static memory cell, the method comprising: providing a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 ; forming a buried n-type layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a gate, a memory node having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 , and the memory node being closer to the buried n-type layer than the digit line node; forming layers relative to the memory node to define, in combination with the memory node, a resonant tunnel diode, one of the layers defining a terminal for the resonant tunnel diode; applying a first voltage to the terminal for the resonant tunnel diode; applying a second voltage to the buried n-type layer, the second voltage being lower than the first voltage; and applying a third voltage to the substrate, the third voltage being between the first voltage and the second voltage.
Claim 8
Independent Claim
209 words
A method of manufacturing and operating a static memory cell, the method comprising: providing a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 ; forming a buried n-type layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a gate, a memory node having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 , and the memory node being closer to the buried n-type layer than the digit line node; forming layers relative to the memory node to define, in combination with the memory node, a resonant tunnel diode, one of the layers defining a terminal for the resonant tunnel diode; applying a first voltage to the terminal for the resonant tunnel diode; applying a second voltage to the buried n-type layer, the second voltage being lower than the first voltage; and applying a third voltage to the substrate, the third voltage being between the first voltage and the second voltage.
Claim 9
Dependent Claim
67 words
A method in accordance with claim 6 wherein the forming of layers relative to the memory node comprises forming a first, insulative, layer on the source, forming a second, conductive, layer on the first layer, forming a third, insulative, layer on the third layer, and forming a fourth, conductive, layer on the third layer, and wherein the fourth layer defines the terminal of the resonant tunnel diode.
Claim 10
Dependent Claim
148 words
A semiconductor processing method of manufacturing a static memory cell, the method comprising: providing a semiconductor substrate of a first conductivity type; forming a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type, and the buried layer having an average dopant concentration of at least 1×10 19 ions/cm 3 ; forming a transistor relative to the substrate over the buried layer, the transistor having a channel of the second conductivity type, forming the transistor comprising forming a gate, a memory node having an average dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average dopant concentration of at least 1×10 19 ions/cm 3 ; and forming alternating layers of insulative and conductive material relative to the memory node to define, in combination with the memory node, a resonant tunnel diode.
Claim 11
Dependent Claim
148 words
A semiconductor processing method of manufacturing a static memory cell, the method comprising: providing a semiconductor substrate of a first conductivity type; forming a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type, and the buried layer having an average dopant concentration of at least 1×10 19 ions/cm 3 ; forming a transistor relative to the substrate over the buried layer, the transistor having a channel of the second conductivity type, forming the transistor comprising forming a gate, a memory node having an average dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average dopant concentration of at least 1×10 19 ions/cm 3 ; and forming alternating layers of insulative and conductive material relative to the memory node to define, in combination with the memory node, a resonant tunnel diode.
Claim 12
Dependent Claim
23 words
A semiconductor processing method in accordance with claim 8 wherein the first conductivity type is positive, and the second conductivity type is negative.
Claim 13
Dependent Claim
23 words
A semiconductor processing method in accordance with claim 8 wherein the first conductivity type is negative, and the second conductivity type is positive.
Claim 14
Dependent Claim
31 words
A semiconductor processing method in accordance with claim 8 wherein forming the memory node comprises forming a memory node having a lowermost portion which is ≦0.1 micron above the buried layer.
Claim 15
Dependent Claim
31 words
A semiconductor processing method in accordance with claim 8 wherein forming the memory node comprises forming a memory node having a lowermost portion which is ≦0.4 micron above the buried layer.
Claim 16
Dependent Claim
32 words
A semiconductor processing method in accordance with claim 8 wherein providing the substrate comprises providing a substrate including material having an average dopant concentration of at least 1×10 16 ions/cm 3 .
Claim 17
Dependent Claim
57 words
A semiconductor processing method in accordance with claim 8 wherein forming the alternating layers relative to the memory node comprises stacking alternating layers of silicon and silicon oxide on the source, including two layers of silicon and two layers of silicon oxide, one of the layers of silicon oxide being in junction relation to the memory node.
Claim 18
Dependent Claim
125 words
A semiconductor processing method of manufacturing a static random access memory cell, the method comprising: forming a semiconductor substrate of a first conductivity type; forming a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; forming a transistor over the buried layer, with a source of the second conductivity type, a gate, and a drain of the second conductivity type, the forming of the transistor comprising providing the source with a depth in the substrate greater than the depth of the drain; and forming alternating layers of insulative and conductive material relative to the source, including two conductive layers and two insulative layers, with one of the insulative layers in junction relation to the source.
Claim 19
Dependent Claim
125 words
A semiconductor processing method of manufacturing a static random access memory cell, the method comprising: forming a semiconductor substrate of a first conductivity type; forming a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; forming a transistor over the buried layer, with a source of the second conductivity type, a gate, and a drain of the second conductivity type, the forming of the transistor comprising providing the source with a depth in the substrate greater than the depth of the drain; and forming alternating layers of insulative and conductive material relative to the source, including two conductive layers and two insulative layers, with one of the insulative layers in junction relation to the source.
Claim 20
Dependent Claim
26 words
A semiconductor processing method in accordance with claim 15 wherein the source is formed with a lowermost portion which is ≦0.4 micron above the buried layer.
Claim 21
Dependent Claim
26 words
A semiconductor processing method in accordance with claim 15 wherein the source is formed with a lowermost portion which is ≦0.1 micron above the buried layer.
Claim 22
Dependent Claim
29 words
A semiconductor processing method in accordance with claim 15 wherein the substrate is formed of material having an average dopant concentration of at least 1×10 16 ions/cm 3 .
Claim 23
Dependent Claim
28 words
A semiconductor processing method in accordance with claim 15 wherein the forming of the layers relative to the source comprises forming alternating layers of silicon and silicon oxide.
Claim 24
Dependent Claim
41 words
A semiconductor processing method in accordance with claim 15 wherein the drain is formed with a dose of n-type material and the source is formed with a dose of n-type material greater than the dose of n-type material for the drain.
Claim 25
Independent Claim
89 words
A method of manufacturing a static memory cell, the method comprising: forming a transistor in a semiconductor substrate, with a gate, a first n+ region having a depth in the substrate, and a second n+ region having a depth in the substrate greater than the depth of the first n+ region; forming an n+ buried layer below the second n+ region; and forming alternating layers of insulative and conductive material relative to the second n+ region to define, in combination with the second n+ region, a resonant tunnel diode.
Claim 26
Independent Claim
89 words
A method of manufacturing a static memory cell, the method comprising: forming a transistor in a semiconductor substrate, with a gate, a first n+ region having a depth in the substrate, and a second n+ region having a depth in the substrate greater than the depth of the first n+ region; forming an n+ buried layer below the second n+ region; and forming alternating layers of insulative and conductive material relative to the second n+ region to define, in combination with the second n+ region, a resonant tunnel diode.
Claim 27
Dependent Claim
61 words
A method of manufacturing a static memory cell in accordance with claim 21 wherein forming the alternating layers relative to the second n+ region comprises forming alternating layers of silicon and silicon oxide on the source, including two layers of silicon and two layers of silicon oxide, with one of the layers of silicon oxide in junction relation to the source.
Claim 28
Independent Claim
89 words
A method of manufacturing a static memory cell, the method comprising: forming a transistor in a semiconductor substrate, with a gate, a first p+ region having a depth in the substrate, and a second p+ region having a depth in the substrate greater than the depth of the first p+ region; forming a p+ buried layer below the second p+ region; and forming alternating layers of insulative and conductive material relative to the second p+ region to define, in combination with the second p+ region, a resonant tunnel diode.
Claim 29
Independent Claim
89 words
A method of manufacturing a static memory cell, the method comprising: forming a transistor in a semiconductor substrate, with a gate, a first p+ region having a depth in the substrate, and a second p+ region having a depth in the substrate greater than the depth of the first p+ region; forming a p+ buried layer below the second p+ region; and forming alternating layers of insulative and conductive material relative to the second p+ region to define, in combination with the second p+ region, a resonant tunnel diode.
Claim 30
Dependent Claim
62 words
A method of manufacturing a static memory cell in accordance with claim 21 wherein forming the alternating layers relative to the second p+ region comprises forming alternating layers of silicon and silicon oxide on the p+ region, including two layers of silicon and two layers of silicon oxide, with one of the layers of silicon oxide in junction relation to the source.
Claim 31
Independent Claim
206 words
A method of manufacturing and operating a static memory cell, the method comprising: providing an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 ; forming a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; forming a p-channel transistor relative to the substrate over the buried p-type layer, the p-channel transistor having a gate, a memory node having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 , and the memory node being closer to the buried p-type layer than the digit line node; forming layers relative to the memory node to define, in combination with the memory node, a resonant tunnel diode, one of the layers defining a terminal for the resonant tunnel diode; applying a first voltage to the substrate; applying a second voltage to the buried n-type layer, the second voltage being above the first voltage; and applying a third voltage to the terminal for the resonant tunnel diode, the third voltage being lower than the first voltage.
Claim 32
Independent Claim
206 words
A method of manufacturing and operating a static memory cell, the method comprising: providing an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 ; forming a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; forming a p-channel transistor relative to the substrate over the buried p-type layer, the p-channel transistor having a gate, a memory node having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 , and the memory node being closer to the buried p-type layer than the digit line node; forming layers relative to the memory node to define, in combination with the memory node, a resonant tunnel diode, one of the layers defining a terminal for the resonant tunnel diode; applying a first voltage to the substrate; applying a second voltage to the buried n-type layer, the second voltage being above the first voltage; and applying a third voltage to the terminal for the resonant tunnel diode, the third voltage being lower than the first voltage.
Claim 33
Dependent Claim
64 words
A method in accordance with claim 25 wherein the forming of layers relative to the memory node comprises forming alternating layers of insulative and conductive material relative to the source, including two conductive layers and two insulative layers, the layers including a lower insulative layer in junction relation to the source and an upper conductive layer defining the terminal for the resonant tunnel diode.
Claim 34
Independent Claim
63 words
A method of manufacturing static memory cell, the method consisting essentially of: forming a buried layer of n-type material in a substrate; forming an n-channel MOSFET having a gate, a drain, and a source, with the source above the buried layer; and forming alternating layers of insulative and conductive material relative to the source to define, with the source, a resonant tunnel diode.
Claim 35
Independent Claim
63 words
A method of manufacturing static memory cell, the method consisting essentially of: forming a buried layer of n-type material in a substrate; forming an n-channel MOSFET having a gate, a drain, and a source, with the source above the buried layer; and forming alternating layers of insulative and conductive material relative to the source to define, with the source, a resonant tunnel diode.
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| 3.5 Years (Year 4) | 2002-11-01 | 2003-05-03 | 2003-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-01 | 2007-05-03 | 2007-11-02 | $3760.00 | Window Closed / Lapsed |
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