High performance mosfet transistor fabrication technique

Claim 2

A semiconductor process comprising: providing a semiconductor substrate; forming a gate dielectric layer on an upper surface of said semiconductor substrate; depositing a conductive layer on an upper surface of said gate dielectric layer; implanting a nitrogen bearing impurity distribution into said conductive layer, wherein said implanting of said nitrogen bearing impurity distribution is accomplished such that a peak impurity concentration of said nitrogen bearing impurity distribution is located at or above a midpoint in said conductive gate layer, and wherein a lower tail of said nitrogen bearing impurity distribution is located within said conductive gate layer whereby said nitrogen bearing impurity distribution is substantially prevented from entering said semiconductor substrate; subsequent to said implanting a nitrogen bearing impurity distribution, patterning said conductive layer to produce a conductive gate structure, wherein said conductive gate structure is aligned over a channel region of said semiconductor substrate; and simultaneously implanting a first source/drain impurity distribution into said semiconductor substrate wherein said conductive gate structure acts as an implant mask during said implanting whereby said first impurity distribution is laterally disposed on either side of said channel region.

Claim 3

The process of claim 1, wherein said semiconductor substrate comprises a single crystal silicon wafer including a p-type epitaxial layer formed on a p+ silicon bulk, wherein a resistivity of said epitaxial layer is in the range of approximately 10 to 15 Ω-cm.

Claim 4

The process of claim 1, wherein the step of forming said gate dielectric layer comprises growing a thermal oxide by immersing said semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 500 to 900° C.

Claim 5

The process of claim 1, wherein an implant dose for said implanting of said first source/drain impurity distribution is less than approximately 1×10 15 atoms/cm 2 .

Claim 6

The process of claim 1, further comprising: forming a drain mask over an LDD region and a drain region of said semiconductor substrate, wherein said LDD region is a part of said first source/drain impurity distribution, and wherein said LDD region is laterally disposed between said drain region and said channel region of said semiconductor substrate; subsequent to said implanting a first source/drain impurity distribution, implanting a source impurity distribution into said semiconductor substrate wherein said source impurity distribution is aligned with said conductive gate structure and further whereby said source impurity distribution is substantially excluded from said channel region, said LDD region, and said drain region of said semiconductor substrate; removing said drain mask from said semiconductor substrate; forming spacer structures on respective sidewalls of said conductive gate structure, wherein said spacer structures mask a region of said semiconductor substrate upper surface proximal to said channel region including said LDD region; implanting a drain impurity distribution into said semiconductor substrate, wherein said conductive gate structure and said spacer structures mask said drain impurity distribution whereby said drain impurity distribution is substantially excluded from said channel region and said LDD region.

Claim 7

The process of claim 5, wherein said drain mask comprises photoresist.

Claim 8

The process of claim 5, wherein an implant dose for said implanting of said source impurity distribution is in the range of approximately 1×10 15 to 7×10 15 atoms/cm 2 .

Claim 9

The process of claim 5, wherein an implant dose for said implanting of said drain impurity distribution is greater than approximately 1×10 15 atoms/cm 2 .

Claim 10

A semiconductor process comprising: providing a semiconductor substrate; forming a gate dielectric layer on an upper surface of said semiconductor substrate; depositing a conductive layer on an upper surface of said gate dielectric layer; implanting a nitrogen bearing impurity distribution into said conductive layer; patterning said conductive layer to produce a conductive gate structure, wherein said conductive gate structure is aligned over a channel region of said semiconductor substrate; simultaneously implanting a first source/drain impurity distribution into said semiconductor substrate wherein said conductive gate structure acts as an implant mask during said implanting whereby said first source/drain impurity distribution is laterally disposed on either side of said channel region; forming a drain mask over an LDD region and a drain region of said semiconductor substrate, wherein said LDD region is part of said first source/drain impurity distribution, and wherein said LDD region is laterally disposed between said drain region and said channel region of said semiconductor substrate; subsequent to said implanting a first source/drain impurity distribution, implanting a source impurity distribution into said semiconductor substrate wherein said source impurity distribution is aligned with said conductive gate structure and further whereby said source impurity distribution is substantially excluded from said channel region, said LDD region, and said drain region of said semiconductor substrate; removing said drain mask from said semiconductor substrate; forming spacer structures on respective sidewalls of said conductive gate structure, wherein said spacer structures mask a region of said semiconductor substrate upper surface proximal to said channel region including said LDD region; and implanting a drain impurity distribution into said semiconductor substrate, wherein said conductive gate structure and said spacer structures mask said drain impurity distribution whereby said drain impurity distribution is substantially excluded from said channel region and said LDD region.

Claim 11

A semiconductor process comprising: providing a semiconductor substrate; forming a gate dielectric layer on an upper surface of said semiconductor substrate; depositing a conductive layer on an upper surface of said gate dielectric layer; implanting a nitrogen bearing impurity distribution into said conductive layer; patterning said conductive layer to produce a conductive gate structure, wherein said conductive gate structure is aligned over a channel region of said semiconductor substrate; simultaneously implanting a first source/drain impurity distribution into said semiconductor substrate wherein said conductive gate structure acts as an implant mask during said implanting whereby said first source/drain impurity distribution is laterally disposed on either side of said channel region; forming a drain mask over an LDD region and a drain region of said semiconductor substrate, wherein said LDD region is part of said first source/drain impurity distribution, and wherein said LDD region is laterally disposed between said drain region and said channel region of said semiconductor substrate; subsequent to said implanting a first source/drain impurity distribution, implanting a source impurity distribution into said semiconductor substrate wherein said source impurity distribution is aligned with said conductive gate structure and further whereby said source impurity distribution is substantially excluded from said channel region, said LDD region, and said drain region of said semiconductor substrate; removing said drain mask from said semiconductor substrate; forming spacer structures on respective sidewalls of said conductive gate structure, wherein said spacer structures mask a region of said semiconductor substrate upper surface proximal to said channel region including said LDD region; and implanting a drain impurity distribution into said semiconductor substrate, wherein said conductive gate structure and said spacer structures mask said drain impurity distribution whereby said drain impurity distribution is substantially excluded from said channel region and said LDD region.

Claim 12

The process of claim 9, wherein said implanting of said nitrogen bearing impurity distribution is accomplished such that a peak impurity concentration of said nitrogen bearing impurity distribution is located below a midpoint in said conductive gate layer and further wherein a lower tail of said impurity distribution extends within an upper region of said semiconductor substrate.

Claim 13

The process of claim 9, wherein said implanting of said nitrogen bearing impurity distribution is accomplished such that a peak impurity concentration of said nitrogen bearing impurity distribution is located at or above a midpoint in said conductive gate layer, and wherein a lower tail of said impurity is located within said conductive gate layer whereby said impurity distribution is substantially prevented from entering said semiconductor substrate.

Claim 14

The process of claim 9, wherein an implant dose for said implanting of said first source/drain impurity distribution is less than approximately 1×10 15 atoms/cm 2 .

Claim 15

The process of claim 12, wherein an implant dose for said implanting of said source impurity distribution is in the range of approximately 1×10 15 to 7×10 15 atoms/cm 2 .

Claim 16

The process of claim 13, wherein an implant dose for said implanting of said drain impurity distribution is greater than approximately 1×10 15 atoms/cm 2 .