Method of producing an EEPROM semiconductor structure

Claim 1

A method of producing an EEPROM semiconductor structure with a resistor, a thin-film transistor, a capacitor, a memory transistor, and a transistor, the method which comprises: providing a semiconductor substrate of a first conductivity type, and forming a field oxide in a first partial region of the substrate and a gate oxide in a second partial region of the substrate; depositing a first polysilicon layer on the substrate and subsequently structuring the first polysilicon layer to form silicon structures for a resistor, for a thin-film transistor, and for a capacitor on the field oxide, and a silicon structure for a memory transistor on the gate oxide; masking the silicon structures for the resistor and the thin-film transistor with a mask and doping the silicon structures for the capacitor and the memory transistor with a dopant of a second conductivity type; removing the mask, and depositing and structuring an interpolydielectric on the silicon structures of the thin-film transistor, the capacitor, and the memory transistor, and depositing polysilicon on the interpolydielectric and structuring the polysilicon to form a second silicon structure for the transistor; masking the regions for the thin-film transistor and the capacitor with a further mask, and, in a second implantation step, performing an LDD implantation in the region of the memory transistor and the transistor, and simultaneously doping the silicon structure for the resistor; removing the further mask; subsequently masking a center region of the resistor; and, in a third implantation step, performing a source-drain implantation with a dopant of the second conductivity type, and simultaneously doping outer regions of the silicon structures for the resistor and the thin-film transistor.

Claim 2

A method of producing an EEPROM semiconductor structure with a resistor, a thin-film transistor, a capacitor, a memory transistor, and a transistor, the method which comprises: providing a semiconductor substrate of a first conductivity type, and forming a field oxide in a first partial region of the substrate and a gate oxide in a second partial region of the substrate; depositing a first polysilicon layer on the substrate and subsequently structuring the first polysilicon layer to form silicon structures for a resistor, for a thin-film transistor, and for a capacitor on the field oxide, and a silicon structure for a memory transistor on the gate oxide; masking the silicon structures for the resistor and the thin-film transistor with a mask and doping the silicon structures for the capacitor and the memory transistor with a dopant of a second conductivity type; removing the mask, and depositing and structuring an interpolydielectric on the silicon structures of the thin-film transistor, the capacitor, and the memory transistor, and depositing polysilicon on the interpolydielectric and structuring the polysilicon to form a second silicon structure for the transistor; masking the regions for the thin-film transistor and the capacitor with a further mask, and, in a second implantation step, performing an LDD implantation in the region of the memory transistor and the transistor, and simultaneously doping the silicon structure for the resistor; removing the further mask; subsequently masking a center region of the resistor; and, in a third implantation step, performing a source-drain implantation with a dopant of the second conductivity type, and simultaneously doping outer regions of the silicon structures for the resistor and the thin-film transistor.