Method and apparatus for generating planarizing pattern and semiconductor integrated circuit device

Claim 3

A method of generating a planarizing pattern according to claim 1, wherein said dummy-pattern generating step includes the steps of: enlarging said wiring pattern by a first specified amount to generate an enlarged wiring pattern; consecutively placing said simple geometric figures to generate a dummy original pattern; and generating said dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said dummy original pattern with said enlarged wiring pattern and said planarizing-pattern generating step includes the steps of: reducing said dummy pattern by a second specified amount to generate a reduced dummy pattern; and enlarging said reduced dummy pattern by said second specified amount to generate said planarizing pattern.

Claim 4

A method of generating a planarizing pattern according to claim 1, wherein said dummy-pattern generating step includes the steps of: graphically inverting said wiring pattern to generate an inverted wiring pattern; reducing said inverted wiring pattern by a first specified amount to generate a reduced inverted wiring pattern; consecutively placing said simple geometric figures to generate a dummy original pattern; and generating said dummy pattern by figure logical-AND operation for leaving only an overlapping portion of said dummy original pattern with said reduced inverted wiring pattern and said planarizing-pattern generating step includes the steps of: reducing said dummy pattern by a second specified amount to generate a reduced dummy pattern; and enlarging said reduced dummy pattern by said second specified amount to generate said planarizing pattern.

Claim 7

A method of generating a planarizing pattern according to claim 4, wherein said first-dummy-pattern generating step includes the steps of: enlarging said wiring pattern by a first specified amount to generate an enlarged wiring pattern; consecutively placing said simple geographic figures in said wiring layer to generate a first dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said first dummy original pattern with said enlarged wiring pattern, said second-dummy-pattern generating step includes the steps of: reducing said first dummy pattern by a second specified amount to generate a first reduced dummy pattern; and enlarging said first reduced dummy pattern by said second specified amount to generate said second dummy pattern, said third-dummy-pattern generating step includes the steps of: parallel-shifting the simple geometric figures composing said first dummy original pattern to generate a second dummy original pattern; enlarging said second dummy pattern by a third specified amount to generate an enlarged dummy pattern; and generating said third dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said second dummy original pattern with said enlarged wiring pattern and with said enlarged dummy pattern, said fourth-dummy-pattern generating step includes the steps of: reducing said third dummy pattern by a fourth specified amount to generate a second reduced dummy pattern; and enlarging said second reduced dummy pattern by said fourth specified amount to generate said fourth dummy pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said second dummy pattern with said fourth dummy pattern.

Claim 10

A method of generating a planarizing pattern according to claim 6, wherein said first-dummy-pattern generating step includes the steps of: enlarging said wiring pattern by a first specified amount to generate a first enlarged wiring pattern; enlarging said wiring pattern by a second specified amount larger than said first specified amount to generate a second enlarged wiring pattern; inverting said second enlarged wiring pattern to generate an inverted pattern; consecutively placing said simple geometric figures to generate a dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said dummy original pattern with said first enlarged wiring pattern and with said inverted pattern, said second-dummy-pattern generating step includes the step of generating said second dummy pattern composed of said inverted pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said first dummy pattern with said second dummy pattern.

Claim 11

A method of generating a planarizing pattern according to claim 6, wherein said first-dummy-pattern generating step includes the steps of: enlarging said wiring pattern by a first specified amount to generate an enlarged wiring pattern; inverting said wiring pattern to generate an inverted pattern; reducing said inverted pattern by a second specified amount larger than said first specified amount to generate a reduced inverted pattern; consecutively placing said simple geometric figures to generate a dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said dummy original pattern with said enlarged wiring pattern and with said reduced inverted pattern, said second-dummy-pattern generating step includes the step of generating said second dummy pattern composed of said reduced inverted pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said first dummy pattern with said second dummy pattern.

Claim 12

A method of generating a planarizing pattern according to claim 6, wherein said first-dummy-pattern generating step includes the steps of: enlarging said wiring pattern by a first specified amount to generate a first enlarged wiring pattern; enlarging said wiring pattern by a second specified amount larger than said first specified amount to generate a second enlarged wiring pattern; inverting said second enlarged wiring pattern to generate a first inverted pattern; reducing said first inverted pattern by a third specified amount to generate a reduced inverted pattern; enlarging said reduced inverted pattern by said third specified amount to generate a second inverted pattern; consecutively placing said simple geometric figures to generate a dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said dummy original pattern with said first enlarged wiring pattern and with said second inverted pattern, said second-dummy-pattern generating step includes the step of generating said second dummy pattern composed of said second inverted pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said first dummy pattern with said second dummy pattern.

Claim 15

A method of generating a planarizing pattern according to claim 10, wherein said first-dummy-pattern generating step includes the steps of: enlarging said wiring pattern by a first specified amount to generate a first enlarged wiring pattern; enlarging said wiring pattern by a second specified amount larger than said first specified amount to generate a second enlarged wiring pattern; inverting said second enlarged wiring pattern to generate an inverted pattern; consecutively placing said first simple geometric figures to generate a first dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said first dummy original pattern with said first enlarged wiring pattern and with said inverted pattern, said second-dummy-pattern generating step includes the steps of: consecutively placing said second simple geometric figures to generate a second dummy original pattern; and generating said second dummy pattern by figure logical-AND operation for leaving only an overlapping portion of said second dummy original pattern with said inverted pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said first dummy pattern with said second dummy pattern.

Claim 18

A method of generating a planarizing pattern according to claim 12, wherein said first-dummy-pattern generating step includes the steps of: enlarging said first wiring pattern by a first specified amount to generate a first enlarged wiring pattern; enlarging said second wiring pattern by a second specified amount to generate a second enlarged wiring pattern; generating a synthetical pattern by figure logical-OR operation for combining said first enlarged wiring pattern with said second enlarged wiring pattern; inverting said synthetical pattern to generate an inverted pattern; consecutively placing said simple geometric figures to generate a dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said dummy original pattern with said first enlarged wiring pattern and with said inverted pattern, said second-dummy-pattern generating step includes the step of generating said second dummy pattern composed of said inverted pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said first dummy pattern with said second dummy pattern.

Claim 21

A method of generating a planarizing pattern according to claim 14, wherein said first-dummy-pattern generating step includes the steps of: enlarging said first wiring pattern by a first specified amount to generate a first enlarged wiring pattern; enlarging said second wiring pattern by a second specified amount to generate a second enlarged wiring pattern; generating a synthetical pattern by figure logical-OR operation for combining said first enlarged wiring pattern with said second enlarged wiring pattern; inverting said synthetical pattern to generate an inverted pattern; consecutively placing said first simple geometric figures to generate a first dummy original pattern; and generating said first dummy pattern by figure logical-MINUS operation for deleting an overlapping portion of said first dummy original pattern with said first enlarged wiring pattern and with said inverted pattern, said second-dummy-pattern generating step includes the steps of: consecutively placing said second simple geometric figures to generate a second dummy original pattern; and generating said second dummy pattern by figure logical-AND operation for leaving only an overlapping portion of said second dummy original pattern with said inverted pattern, and said planarizing-pattern generating step includes the step of generating said planarizing pattern by figure logical-OR operation for combining said first dummy pattern with said second dummy pattern.

Claim 34

A semiconductor integrated circuit device comprising: a wiring pattern formed in a wiring layer on a semiconductor substrate; a first planarizing pattern composed of a group of identical simple geometric figures and formed in a region of said wiring layer lying at a first specified distance or further away from said wiring pattern and at a second specified distance from or closer to said wiring pattern, said second specified distance being larger than said first specified distance; a second planarizing pattern composed of at least one geometric figure larger than said simple geometric figure and formed in a region of said wiring layer lying at said second specified distance or further away from said wiring pattern; and an interlayer insulating film formed over said wiring pattern, said first planarizing pattern, and said second planarizing pattern.

Claim 35

A semiconductor integrated circuit device comprising: a wiring pattern formed in a wiring layer on a semiconductor substrate; a first planarizing pattern composed of a group of identical simple geometric figures and formed in a region of said wiring layer lying at a first specified distance or further away from said wiring pattern and at a second specified distance from or closer to said wiring pattern, said second specified distance being larger than said first specified distance; a second planarizing pattern composed of at least one geometric figure larger than said simple geometric figure and formed in a region of said wiring layer lying at said second specified distance or further away from said wiring pattern; and an interlayer insulating film formed over said wiring pattern, said first planarizing pattern, and said second planarizing pattern.

Claim 36

A semiconductor integrated circuit device comprising: a first wiring pattern formed in a first wiring layer on a semiconductor substrate; a second wiring pattern formed in a second wiring layer overlying or underlying said first wiring layer on said semiconductor substrate; a first planarizing pattern composed of a group of identical simple geometric figures and formed in a region of said first wiring layer lying at a first specified distance or further away from said first wiring pattern, at a second specified distance from or closer to said first wiring pattern, said second specified distance being larger than said first specified distance, and at a third specified distance from or closer to said second wiring pattern; a second planarizing pattern composed of at least one geometric figure larger than said simple geometric figure and formed in a region of said first wiring layer lying at said second specified distance or further away from said first wiring pattern and at said third specified distance or further away from said second wiring pattern; and an interlayer insulating film formed between said first wiring pattern, said first planarizing pattern, and said second planarizing pattern each formed in said first wiring layer and said second wiring pattern formed in said second wiring layer.

Claim 37

A semiconductor integrated circuit device comprising: a first wiring pattern formed in a first wiring layer on a semiconductor substrate; a second wiring pattern formed in a second wiring layer overlying or underlying said first wiring layer on said semiconductor substrate; a first planarizing pattern composed of a group of identical simple geometric figures and formed in a region of said first wiring layer lying at a first specified distance or further away from said first wiring pattern, at a second specified distance from or closer to said first wiring pattern, said second specified distance being larger than said first specified distance, and at a third specified distance from or closer to said second wiring pattern; a second planarizing pattern composed of at least one geometric figure larger than said simple geometric figure and formed in a region of said first wiring layer lying at said second specified distance or further away from said first wiring pattern and at said third specified distance or further away from said second wiring pattern; and an interlayer insulating film formed between said first wiring pattern, said first planarizing pattern, and said second planarizing pattern each formed in said first wiring layer and said second wiring pattern formed in said second wiring layer.