Patent US5969394A successfully refreshed from Google Patents.
US5969394A
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Method and structure for high aspect gate and short channel length insulated gate field effect transistors
Assignee: GlobalFoundries Inc
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Filing: 1997-12-18
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Granted: 1999-10-19
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Expires: 2017-12-18
Abstract
Abstract A method and structure are provided for an IGFET which has a short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Also the invention includes a dielectric layer with a high dielectric constant value (K) to prolong the longevity of the device. A lightly doped drain region similarly preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.
Inventors
- 👤 Mark I. Gardner
- 👤 Daniel Kadosh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:09
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10P; H10P32/00; H10P32/10; H10P32/12; H10P32/17; H10P32/171; H10D30/0212; H10D64/60; H10D64/66; H10D64/68
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
67 words
A device comprising: a dielectric layer on a surface of a semiconductor substrate; a gate on a surface of the dielectric layer, the gate having opposing sides, wherein a portion of the gate is greater in length than the dielectric layer, and extends past the dielectric layer underneath on one of the opposing sides; a source region within the substrate; and a drain region within the substrate.
Claim 2
Independent Claim
67 words
A device comprising: a dielectric layer on a surface of a semiconductor substrate; a gate on a surface of the dielectric layer, the gate having opposing sides, wherein a portion of the gate is greater in length than the dielectric layer, and extends past the dielectric layer underneath on one of the opposing sides; a source region within the substrate; and a drain region within the substrate.
Claim 3
Dependent Claim
31 words
The device of claim 1 further comprising a lightly doped drain region within the substrate and underneath the portion of the gate and is longer in length than the dielectric layer.
Claim 4
Dependent Claim
18 words
The device of claim 1 wherein the dielectric layer material comprises a material having a high dielectric constant.
Claim 5
Dependent Claim
29 words
The device of claim 1 wherein the length difference between the gate and the dielectric layer is formed by applying an etchant to the dielectric layer underneath the gate.
Claim 6
Dependent Claim
27 words
The device of claim 1 wherein the drain region is disposed adjacent to the portion of the gate which is greater in length than the dielectric layer.
Claim 7
Dependent Claim
18 words
The device of claim 1 wherein the source region and the drain region are self-aligned with the gate.
Claim 8
Dependent Claim
16 words
The device of claim 2 wherein the lightly doped drain region is formed from Arsenic (As).
Claim 9
Dependent Claim
24 words
The device of claim 1 further comprising a salicidation layer on the source region, the drain and lightly doped drain regions, and the gate.
Claim 10
Dependent Claim
104 words
An information handling system comprising: a central processing unit; a random access memory; and a system bus for communicatively coupling the central processing unit and the random access memory, said information handling system further including at least one device comprising: a dielectric layer on a surface of a semiconductor substrate; a gate on a surface of the dielectric layer, the gate having opposing sides, wherein a portion of the gate is greater in length than the dielectric layer and extends past the dielectric layer underneath on one of the opposing sides; a source region within the substrate; and a drain region within the substrate.
Claim 11
Dependent Claim
104 words
An information handling system comprising: a central processing unit; a random access memory; and a system bus for communicatively coupling the central processing unit and the random access memory, said information handling system further including at least one device comprising: a dielectric layer on a surface of a semiconductor substrate; a gate on a surface of the dielectric layer, the gate having opposing sides, wherein a portion of the gate is greater in length than the dielectric layer and extends past the dielectric layer underneath on one of the opposing sides; a source region within the substrate; and a drain region within the substrate.
Claim 12
Dependent Claim
32 words
The information handling system of claim 9 further comprising a lightly doped drain within the substrate and underneath the portion of the gate and is longer in length than the dielectric layer.
Claim 13
Dependent Claim
19 words
The information handling system of claim 9 wherein the dielectric layer comprises a material having a high dielectric constant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-18 | 2003-04-19 | 2003-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-18 | 2007-04-19 | 2007-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-18 | 2011-04-19 | 2011-10-19 | $7700.00 | Window Closed / Lapsed |