US5965939A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and a method of manufacture
Assignee: Samsung Electronics Co Ltd
•
Filing: 1997-04-22
•
Granted: 1999-10-12
•
Expires: 2017-04-22
Abstract
Abstract A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
Inventors
- 👤 Kyeong-tae Kim
- 👤 Yun-Seung Shin
- 👤 Young-hun Park
- 👤 Won-mo Park
- 👤 Ji-hong Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P95/066; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; Y; Y10; Y10S; Y10S438/00; Y10S438/926
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
97 words
A semiconductor device comprising: a semiconductor substrate; a cell array region formed on said semiconductor substrate; a peripheral circuit region formed adjacent said cell array region, wherein a step difference is defined by the respective surfaces of said cell array region and said peripheral circuit region; a dummy pattern formed on and covering substantially all of said peripheral circuit region, thereby compensating for said step difference, said dummy pattern overlapping a portion of said cell array region adjacent said peripheral circuit region; and a planarized insulating layer formed on said dummy pattern and said cell array region.
Claim 2
Dependent Claim
97 words
A semiconductor device comprising: a semiconductor substrate; a cell array region formed on said semiconductor substrate; a peripheral circuit region formed adjacent said cell array region, wherein a step difference is defined by the respective surfaces of said cell array region and said peripheral circuit region; a dummy pattern formed on and covering substantially all of said peripheral circuit region, thereby compensating for said step difference, said dummy pattern overlapping a portion of said cell array region adjacent said peripheral circuit region; and a planarized insulating layer formed on said dummy pattern and said cell array region.
Claim 3
Dependent Claim
21 words
A semiconductor device as in claim 1, wherein said cell array region formed on said semiconductor substrate comprises a conductive pattern.
Claim 4
Dependent Claim
37 words
A semiconductor device as in claim 1, wherein said cell array region comprises a stacked capacitor having a storage electrode, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film.
Claim 5
Dependent Claim
53 words
A semiconductor device as in claim 1, wherein said cell array region is formed on a first portion of said semiconductor substrate and said peripheral circuit region is formed on a second portion of said semiconductor substrates the surface of said first portion being recessed relative to the surface of said second portion.
Claim 6
Dependent Claim
16 words
A semiconductor device as in claim 1, wherein said dummy pattern comprises an inorganic insulating material.
Claim 7
Dependent Claim
18 words
A semiconductor device as in claim 1, wherein said planarized insulating layer is a borophosphosilicate glass (BPSG) layer.
Claim 8
Dependent Claim
193 words
A semiconductor device comprising: a semiconductor substrate; an impurity-doped region formed around the surface portion of said semiconductor substrate; a first insulating layer for defining at least one active region on said semiconductor substrate; a cell array region including a bit line formed on said first insulating layer, a second insulating layer for insulating said bit line, and a capacitor; said capacitor comprising a storage electrode formed on said second insulating layer and electrically connected with said impurity-doped region, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film; a peripheral circuit region formed adjacent said cell array region, with said second insulating layer extending into said peripheral circuit region wherein a step difference is defined by the respective surfaces of said cell array region and said peripheral circuit region; a dummy pattern formed on and covering substantially all of said peripheral circuit region thereby compensating for said step difference,said dummy pattern overlapping a portion of said plate electrode adjacent said peripheral circuit region; and a third insulating layer formed on said dummy pattern and over said cell array region, said third insulating layer being planarized.
Claim 9
Dependent Claim
193 words
A semiconductor device comprising: a semiconductor substrate; an impurity-doped region formed around the surface portion of said semiconductor substrate; a first insulating layer for defining at least one active region on said semiconductor substrate; a cell array region including a bit line formed on said first insulating layer, a second insulating layer for insulating said bit line, and a capacitor; said capacitor comprising a storage electrode formed on said second insulating layer and electrically connected with said impurity-doped region, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film; a peripheral circuit region formed adjacent said cell array region, with said second insulating layer extending into said peripheral circuit region wherein a step difference is defined by the respective surfaces of said cell array region and said peripheral circuit region; a dummy pattern formed on and covering substantially all of said peripheral circuit region thereby compensating for said step difference,said dummy pattern overlapping a portion of said plate electrode adjacent said peripheral circuit region; and a third insulating layer formed on said dummy pattern and over said cell array region, said third insulating layer being planarized.
Claim 10
Dependent Claim
53 words
A semiconductor device as in claim 7, wherein said cell array region is formed on a first portion of said semiconductor substrate and said peripheral circuit region is formed on a second portion of said semiconductor substrate, the surface of said first portion being recessed relative to the surface of said second portion.
Claim 11
Dependent Claim
219 words
A semiconductor device comprising: a semiconductor substrate; an impurity-doped region formed in the surface portion of said semiconductor substrate; a first insulating layer for defining at least one active region on said semiconductor substrate; a cell array region including a bit line formed on said first insulating layer, a second insulating layer for insulating said bit line, and a capacitor; said capacitor comprising a storage electrode formed on said second insulating layer and electrically connected with said impurity-doped region, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film; a peripheral circuit region formed adjacent said cell array region, with said second insulating layer extending into said peripheral circuit region; wherein said cell array region is formed in a recessed region of said semiconductor substrate relative to said peripheral circuit region, the respective surfaces of said cell array region and said peripheral circuit region defining a step difference; a dummy pattern for compensating for said step difference, said dummy pattern being formed on and covering substantially all of said peripheral circuit region and said dummy pattern overlapping a portion of said plate electrode adjacent said peripheral circuit region; and a third insulating layer formed on said dummy pattern and plate electrode of said cell array region, said third insulating layer being planarized.
Claim 12
Dependent Claim
219 words
A semiconductor device comprising: a semiconductor substrate; an impurity-doped region formed in the surface portion of said semiconductor substrate; a first insulating layer for defining at least one active region on said semiconductor substrate; a cell array region including a bit line formed on said first insulating layer, a second insulating layer for insulating said bit line, and a capacitor; said capacitor comprising a storage electrode formed on said second insulating layer and electrically connected with said impurity-doped region, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film; a peripheral circuit region formed adjacent said cell array region, with said second insulating layer extending into said peripheral circuit region; wherein said cell array region is formed in a recessed region of said semiconductor substrate relative to said peripheral circuit region, the respective surfaces of said cell array region and said peripheral circuit region defining a step difference; a dummy pattern for compensating for said step difference, said dummy pattern being formed on and covering substantially all of said peripheral circuit region and said dummy pattern overlapping a portion of said plate electrode adjacent said peripheral circuit region; and a third insulating layer formed on said dummy pattern and plate electrode of said cell array region, said third insulating layer being planarized.
References Cited (Backward Citations)
US4505025A
Cited
US4764483A
Cited
US4882289A
Cited
US5204288A
Cited
US5218219A
Cited
US5386382A
Cited
US5406103A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |