Patent US5964880A successfully refreshed from Google Patents.
US5964880A
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Circuit interface synchronization using slave variable delay loop
Assignee: Intel Corp
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Filing: 1997-12-10
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Granted: 1999-10-12
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Expires: 2017-12-10
Abstract
Abstract A method and apparatus is provided for synchronizing clock signals. The method includes receiving a first reference clock signal, generating a second clock signal, modifying the second clock signal to synchronize a first feedback input clock signal with the first reference clock signal, and modifying the second clock signal to synchronize a second feedback input clock signal with a second reference clock signal. The apparatus includes a phase aligning device having a first reference clock input adapted to receive a first reference clock signal, a first feedback input, and an output. A fixed delay device is coupled between the output of the phase aligning device and the first feedback input of the phase aligning device. A slave loop is coupled to the output of the phase aligning device.
Inventors
- 👤 Jonathan H. Liu
- 👤 Michael J. Allen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:59
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
120 words
A method for synchronizing clock signals, comprising: receiving a first reference clock signal; receiving a second reference clock signal; generating a phase-locked or delay-locked output of the first reference clock signal; delaying the output by a first delay interval to generate a first clock output signal, which is also coupled back as feedback for aligning the output to the first reference clock signal delaying the output by a second delay interval to generate a second clock output signal; detecting a phase difference between the second clock output signal and the second reference clock signal to determine skew; generating a correction signal to vary the second delay interval to correct the skew to synchronize the first and second clock output signals.
Claim 2
Independent Claim
120 words
A method for synchronizing clock signals, comprising: receiving a first reference clock signal; receiving a second reference clock signal; generating a phase-locked or delay-locked output of the first reference clock signal; delaying the output by a first delay interval to generate a first clock output signal, which is also coupled back as feedback for aligning the output to the first reference clock signal delaying the output by a second delay interval to generate a second clock output signal; detecting a phase difference between the second clock output signal and the second reference clock signal to determine skew; generating a correction signal to vary the second delay interval to correct the skew to synchronize the first and second clock output signals.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein the receiving of the first and second reference clock signals receives the same reference clock signal as the first and second reference clock signals.
Claim 4
Dependent Claim
30 words
The method of claim 1, wherein the second delay interval has a range of delay calculated as the first interval minus the skew to the first interval plus the skew.
Claim 5
Dependent Claim
23 words
The method of claim 1 further comprising the generation of a plurality of second clock output signals, each having its skew adjusted separately.
Claim 6
Dependent Claim
29 words
The method of claim 1, wherein the delaying the output by the first delay interval includes delaying the output so that the first delay interval is a fixed interval.
Claim 7
Dependent Claim
29 words
The method of claim 5, wherein the delaying the output by the second delay interval includes delaying the output so that the second delay interval is a variable interval.
Claim 8
Dependent Claim
19 words
The method of claim 6, wherein the generating the correction signal adjusts the second delay interval, which is variable.
Claim 9
Dependent Claim
30 words
The method of claim 7, wherein the receiving of the first and second reference clock signals receives the same reference clock signal as the first and second reference clock signals.
Claim 10
Independent Claim
165 words
An apparatus for synchronizing clock signals comprising: a phase aligning circuit coupled to receive a reference clock signal and generate an output signal, which is phase aligned with the reference clock signal; a fixed delay circuit coupled to the phase aligning circuit to receive its output signal and for generating a first clock signal, which is delayed from the output signal by a first delay interval; the first clock signal coupled to a first destination and also coupled as feedback to the phase aligning circuit; a slave circuit coupled to receive the output signal of the phase aligning circuit and for generating a second clock signal to a second destination, wherein the second clock signal is delayed from the output signal by a second delay interval; the slave circuit also coupled to receive the reference clock signal to detect a phase difference between the reference clock signal and the second clock signal and adjusting the second delay to synchronize the first and second clock signals.
Claim 11
Independent Claim
165 words
An apparatus for synchronizing clock signals comprising: a phase aligning circuit coupled to receive a reference clock signal and generate an output signal, which is phase aligned with the reference clock signal; a fixed delay circuit coupled to the phase aligning circuit to receive its output signal and for generating a first clock signal, which is delayed from the output signal by a first delay interval; the first clock signal coupled to a first destination and also coupled as feedback to the phase aligning circuit; a slave circuit coupled to receive the output signal of the phase aligning circuit and for generating a second clock signal to a second destination, wherein the second clock signal is delayed from the output signal by a second delay interval; the slave circuit also coupled to receive the reference clock signal to detect a phase difference between the reference clock signal and the second clock signal and adjusting the second delay to synchronize the first and second clock signals.
Claim 12
Dependent Claim
19 words
The apparatus of claim 9, wherein the slave circuit is actually comprised of a plurality of such slave circuits.
Claim 13
Dependent Claim
20 words
The apparatus of claim 10, wherein the plurality of slave circuits are connected in parallel with respect to each other.
Claim 14
Dependent Claim
20 words
The apparatus of claim 10, wherein the plurality of slave circuits are connected in series with respect to each other.
Claim 15
Dependent Claim
49 words
The apparatus of claim 9, wherein the slave circuit further comprises: a variable delay circuit for introducing the second delay interval which is adjustable; and a phase detector coupled to detect the phase difference and correspondingly adjust the variable delay circuit to synchronize the first and second clock signals.
Claim 16
Dependent Claim
14 words
The apparatus of claim 13, wherein the phase aligning circuit includes a phase-lock loop.
Claim 17
Dependent Claim
14 words
The apparatus of claim 13, wherein the phase aligning circuit includes a delay-lock loop.
Claim 18
Dependent Claim
15 words
The apparatus of claim 13, wherein the fixed delay circuit includes a fixed delay line.
Claim 19
Dependent Claim
43 words
The apparatus of claim 13, wherein the first delay interval is to compensate for a propagation delay of the output signal to the slave circuit and the second delay interval is to adjust for a skew between the first and second clock signals.
Claim 20
Dependent Claim
15 words
The apparatus of claim 13, wherein the variable delay circuit includes a variable delay line.
Claim 21
Dependent Claim
26 words
The apparatus of claim 18, wherein the variable delay line is adjustable over a range of skew values encountered between the first and second clock signals.
Claim 22
Independent Claim
171 words
An apparatus for synchronizing clock signals comprising: a phase aligning circuit coupled to receive a first reference clock signal and generate a reference output signal, which is phase aligned with the first reference clock signal; a fixed delay circuit coupled to the phase aligning circuit to receive its reference output signal and for generating a first clock output signal, which is delayed from the reference output signal by a first delay interval; the first clock output signal also coupled as feedback to the phase aligning circuit; a slave circuit coupled to receive the reference output signal of the phase aligning circuit and for generating a second clock output signal, wherein the second clock output signal is delayed from the reference output signal by a second delay interval; the slave circuit also coupled to receive a second reference clock signal to detect a phase difference between the second reference clock signal and the second clock output signal and adjusting the second delay interval to synchronize the first and second clock output signals.
Claim 23
Independent Claim
171 words
An apparatus for synchronizing clock signals comprising: a phase aligning circuit coupled to receive a first reference clock signal and generate a reference output signal, which is phase aligned with the first reference clock signal; a fixed delay circuit coupled to the phase aligning circuit to receive its reference output signal and for generating a first clock output signal, which is delayed from the reference output signal by a first delay interval; the first clock output signal also coupled as feedback to the phase aligning circuit; a slave circuit coupled to receive the reference output signal of the phase aligning circuit and for generating a second clock output signal, wherein the second clock output signal is delayed from the reference output signal by a second delay interval; the slave circuit also coupled to receive a second reference clock signal to detect a phase difference between the second reference clock signal and the second clock output signal and adjusting the second delay interval to synchronize the first and second clock output signals.
Claim 24
Dependent Claim
62 words
The apparatus of claim 20, wherein the slave circuit further comprises: a variable delay circuit for introducing the second delay interval which is adjustable; and a phase detector coupled to detect the phase difference between the second reference clock signal and the second clock output signal and correspondingly adjust the variable delay circuit to synchronize the first and second clock output signals.
Claim 25
Dependent Claim
19 words
The apparatus of claim 20, wherein the phase aligning circuit includes either a delay-lock loop or a phase-lock loop.
Claim 26
Independent Claim
110 words
An apparatus for synchronizing clock signals comprising: means for aligning the phases of a first clock output signal with a first reference clock signal; means for receiving an output from the means for aligning and delaying the first reference clock signal by a first delay interval to generate the first clock output signal; means for variably delaying the output from the means for aligning by a second delay interval to generate a second clock output signal; and means for determining a phase difference between the second clock output signal and a second reference clock signal to vary the second delay interval to synchronize the first and second clock output signals.
Claim 27
Independent Claim
110 words
An apparatus for synchronizing clock signals comprising: means for aligning the phases of a first clock output signal with a first reference clock signal; means for receiving an output from the means for aligning and delaying the first reference clock signal by a first delay interval to generate the first clock output signal; means for variably delaying the output from the means for aligning by a second delay interval to generate a second clock output signal; and means for determining a phase difference between the second clock output signal and a second reference clock signal to vary the second delay interval to synchronize the first and second clock output signals.
Claim 28
Dependent Claim
17 words
The apparatus of claim 23 wherein the first and second reference clock signals are the same signal.
Claim 29
Dependent Claim
18 words
The apparatus of claim 24, wherein the means for aligning includes a phase-lock loop or a delay-lock loop.
Claim 30
Dependent Claim
15 words
The apparatus of claim 25, wherein the means for delaying includes a fixed delay line.
Claim 31
Dependent Claim
14 words
The apparatus of claim 26, wherein the means for determining includes a phase detector.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |