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US5963737A
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Interupt vectoring for trace exception facility in computer systems
Assignee: International Business Machines Corp
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Filing: 1996-04-18
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Granted: 1999-10-05
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Expires: 2016-04-18
Abstract
Abstract An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.
Inventors
- 👤 Bruce Gerard Mealey
- 👤 James William Van Fleet
- 👤 Michael Stephen Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F11/00; G06F11/30; G06F11/34; G06F11/3466
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
104 words
A trace exception handling mechanism in a processor system having an operating system with a kernel, the processor system executing an application via said kernel, comprising: means in a kernel-extension to said application, for registering a trace exception interrupt handler by a kernel extension, said means including a stored pointer to said a trace exception interrupt handler, means for detecting a trace exception condition in said processor, means in said kernel for checking to see if a trace exception interrupt handler has been registered, and, if so, saving state and then branching to said trace exception interrupt handler in said kernel-extension using said pointer.
Claim 2
Dependent Claim
104 words
A trace exception handling mechanism in a processor system having an operating system with a kernel, the processor system executing an application via said kernel, comprising: means in a kernel-extension to said application, for registering a trace exception interrupt handler by a kernel extension, said means including a stored pointer to said a trace exception interrupt handler, means for detecting a trace exception condition in said processor, means in said kernel for checking to see if a trace exception interrupt handler has been registered, and, if so, saving state and then branching to said trace exception interrupt handler in said kernel-extension using said pointer.
Claim 3
Dependent Claim
15 words
A trace exception handling mechanism according to claim 1 wherein said kernel extension is implementation-dependent.
Claim 4
Dependent Claim
14 words
A trace exception handling mechanism according to claim 1 wherein said kernel is implementation-independent.
Claim 5
Dependent Claim
19 words
A trace exception handling mechanism according to claim 1 wherein said storing of said pointer is in non-paged memory.
Claim 6
Independent Claim
94 words
A method of implementing a trace exception for a processor system having an operating system with a kernel, and executing an application via said kernel comprising the steps of: registering by a kernel-extension for said application a trace exception interrupt handler including storing by said kernel-extension a pointer to said a trace exception interrupt handler, detecting a trace exception condition in said processor, checking, by said kernel to see if said trace exception interrupt handler has been registered, if so, then branching to said trace exception interrupt handler in said kernel-extension using said pointer.
Claim 7
Independent Claim
94 words
A method of implementing a trace exception for a processor system having an operating system with a kernel, and executing an application via said kernel comprising the steps of: registering by a kernel-extension for said application a trace exception interrupt handler including storing by said kernel-extension a pointer to said a trace exception interrupt handler, detecting a trace exception condition in said processor, checking, by said kernel to see if said trace exception interrupt handler has been registered, if so, then branching to said trace exception interrupt handler in said kernel-extension using said pointer.
Claim 8
Dependent Claim
23 words
A method of implementing a trace exception according to claim 5 wherein said kernel extension is implementation-dependent and wherein said kernel is implementation-independent.
Claim 9
Dependent Claim
25 words
A method of implementing a trace exception according to claim 5 including the step of saving state if said trace exception interrupt handler is registered.
Claim 10
Dependent Claim
21 words
A method of implementing a trace exception according to claim 5 wherein said storing of said pointer is in non-paged memory.
Claim 11
Dependent Claim
19 words
A method of implementing a trace exception according to claim 5 wherein said registering is by a kernel extension.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |