Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a plurality of word lines; a pair of bit lines crossing a plurality of said word lines; a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one of said pair of bit lines, wherein each memory cell has an information storing capacitor and a selection MOSFET and each selection MOSFET has a source-drain path provided between a corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line; a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitor, wherein said plate voltage supply circuit receives a power supply voltage and circuit grounding potential to generate said plate voltage set to an intermediate potential of the high and low level potentials given to said pair of bit lines; and a timer circuit which measures a predetermined time which is set corresponding to the time required for the plate voltage to reach the predetermined potential when the power is turned ON; whereby selection of said word lines is inhibited before said predetermined time has passed after the power is turned ON and said inhibiting is canceled after said predetermined time has passed after the power is turned ON.

Claim 3

A semiconductor memory device according to claim 1, wherein the dielectric material film of said information storing capacitor is Ta 2 O 5 m.

Claim 4

A semiconductor memory device according to claim 1, wherein the dielectric material film of said information storing capacitor is BST.

Claim 5

A semiconductor memory device according to claim 1, wherein the dielectric material film of said information storing capacitor is PZT.

Claim 6

A semiconductor memory device according to claim 1, wherein said plate voltage supply circuit comprising: a voltage generating circuit which divides the power supply voltage and the ground potential of the circuit to generate said intermediate voltage; a diode type N-channel first MOSFET which forms a first voltage by level shifting said intermediate voltage as much as the gate source voltage toward the power supply voltage of the circuit; a diode type P-channel second MOSFET which forms a second voltage by level shifting said intermediate voltage as much as gate-source voltage toward the ground potential side of the circuit; an N-channel first output MOSFET having a gate which is connected to said first voltage and a source which is connected to the output terminal; a P-channel second output MOSFET having a gate which is connected to said second voltage and a source which is connected to said output terminal; a P-channel third MOSFET which is provided in the drain side of said first output MOSFET to supply a current; an N-channel fourth MOSFET which is provided in the drain side of said second output MOSFET to supply a current: a P-channel third output MOSFET having a gate which is connected to the drain of said first output MOSFET and a drain which is connected to said output terminal; an N-channel fourth output MOSFET having a gate which is connected to the drain of said second output MOSFET and a drain which is connected to said output terminal; a P-channel first power switch MOSFET which is provided in the source side of said third output MOSFET to provide a comparatively large current when it is turned ON for the constant period after the power is turned ON; a P-channel second power switch MOSFET which is turned ON at least after the predetermined period to provide a comparatively small current; and an N-channel third power switch MOSFET which is provided in the source side of said fourth output MOSFET to provide a comparatively small current.

Claim 7

A semiconductor memory device according to claim 5, wherein said timer circuit measures said predetermined time by counting a clock signal supplied from an external terminal.

Claim 8

A semiconductor memory device comprising: a plurality of word lines; a pair of bit lines crossing a plurality of said word lines; a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one bit line of said pair of bit lines, wherein each memory cell has an information storing capacitor and a selection MOSFET and each selection MOSFET has a source-drain path provided between the corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line; a sense amplifier connected to said pair of bit lines, wherein said sense amplifier supplies high and low level voltages to said pair of bit lines; a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitors, wherein said plate voltage supply circuit is formed to set said plate voltage to an intermediate voltage of said high and low level potentials; and a plate voltage detecting circuit which detects whether said plate voltage has reached a predetermined potential or not after start of operation of said plate voltage supply circuit; wherein said information storing capacitor includes a dielectric material film formed of one of a ferro-dielectric material and a high dielectric material, and wherein access to said memory cells is inhibited until said plate voltage reaches said predetermined potential.

Claim 9

A semiconductor memory device comprising: a plurality of word lines; a pair of bit lines crossing a plurality of said word lines; a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one bit line of said pair of bit lines, wherein each memory cell has an information storing capacitor and a selection MOSFET and each selection MOSFET has a source-drain path provided between the corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line; a sense amplifier connected to said pair of bit lines, wherein said sense amplifier supplies high and low level voltages to said pair of bit lines; a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitors, wherein said plate voltage supply circuit is formed to set said plate voltage to an intermediate voltage of said high and low level potentials; and a plate voltage detecting circuit which detects whether said plate voltage has reached a predetermined potential or not after start of operation of said plate voltage supply circuit; wherein said information storing capacitor includes a dielectric material film formed of one of a ferro-dielectric material and a high dielectric material, and wherein access to said memory cells is inhibited until said plate voltage reaches said predetermined potential.

Claim 10

A semiconductor memory device according to claim 7, wherein said access operation is inhibited by canceling the selected condition of a plurality of said word line.

Claim 11

A semiconductor memory device according to claim 7, wherein an inhibit condition of the access operation may be effectuated by inhibiting the selecting condition of a plurality of said word lines.

Claim 12

A semiconductor memory device comprising: a plurality of word lines; a pair of bit lines crossing a plurality of said word lines; a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one of said pair of bit lines, wherein each memory cell has an information storing capacitor and selection MOSFET and each selection MOSFET has a source-drain path provided between a corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line; a sense amplifier connected to said pair of bit lines, wherein said sense amplifier supplies high and low level potentials to said pair bit lines; a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitors, wherein said plate voltage supply circuit is constituted to output a plate voltage which is set to an intermediate potential of said high and low level potentials; and a timer circuit which measures a predetermined period after the power is turned ON for said semiconductor memory device; wherein said information storing capacitor includes a dielectric material film formed of one of a ferro-dielectric material and a high dielectric material, and wherein access to said memory cell is inhibited until the predetermined time period has expired.

Claim 13

A semiconductor memory device comprising: a plurality of word lines; a pair of bit lines crossing a plurality of said word lines; a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one of said pair of bit lines, wherein each memory cell has an information storing capacitor and selection MOSFET and each selection MOSFET has a source-drain path provided between a corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line; a sense amplifier connected to said pair of bit lines, wherein said sense amplifier supplies high and low level potentials to said pair bit lines; a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitors, wherein said plate voltage supply circuit is constituted to output a plate voltage which is set to an intermediate potential of said high and low level potentials; and a timer circuit which measures a predetermined period after the power is turned ON for said semiconductor memory device; wherein said information storing capacitor includes a dielectric material film formed of one of a ferro-dielectric material and a high dielectric material, and wherein access to said memory cell is inhibited until the predetermined time period has expired.

Claim 14

A semiconductor device comprising: a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a transistor coupled between one electrode of said capacitor and a corresponding bit line; an amplifier coupled to said pair of bit lines, wherein said amplifier operates receiving a first voltage and a second voltage which is larger than said first voltage; a voltage supply circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage; and a timer circuit which measures a predetermined time period after the power for said semiconductor device is turned ON, wherein said plurality of word lines are at a non-selecting level until said predetermined time period has expired.

Claim 15

A semiconductor device comprising: a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a transistor coupled between one electrode of said capacitor and a corresponding bit line; an amplifier coupled to said pair of bit lines, wherein said amplifier operates receiving a first voltage and a second voltage which is larger than said first voltage; a voltage supply circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage; and a timer circuit which measures a predetermined time period after the power for said semiconductor device is turned ON, wherein said plurality of word lines are at a non-selecting level until said predetermined time period has expired.

Claim 16

A semiconductor device comprising: a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a MOSFET having a source-drain path provided between a corresponding bit line and one electrode of said capacitor and a gate connected to a corresponding word line; an amplifier coupled to said pair of bit lines, wherein said amplifier supplies a first voltage and a second voltage which is larger than said first voltage to said pair of bit lines; a voltage supply circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage; and a timer circuit outputting a control signal, wherein said control signal changes from a first level to a second level when a predetermined time period has expired after said voltage supply circuit is activated, wherein said plurality of word lines are at a non-selecting level while said control signal is at said first level.

Claim 17

A semiconductor device comprising: a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a MOSFET having a source-drain path provided between a corresponding bit line and one electrode of said capacitor and a gate connected to a corresponding word line; an amplifier coupled to said pair of bit lines, wherein said amplifier supplies a first voltage and a second voltage which is larger than said first voltage to said pair of bit lines; a voltage supply circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage; and a timer circuit outputting a control signal, wherein said control signal changes from a first level to a second level when a predetermined time period has expired after said voltage supply circuit is activated, wherein said plurality of word lines are at a non-selecting level while said control signal is at said first level.

Claim 18

A semiconductor device comprising: a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a transistor having a current path provided between a corresponding bit line and one electrode of said capacitor; an amplifier coupled to said pair of bit lines, wherein said amplifier senses voltage levels of said pair of bit lines and supplies a first voltage and a second voltage which is larger than said first voltage to said pair of bit lines; a voltage generating circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage; and a timer circuit which measures a predetermined period after said voltage generating circuit changes from a non-activating state to an activating state, wherein access to said memory cells is inhibited until said predetermined period has expired.

Claim 19

A semiconductor device comprising: a plurality of word lines; a pair of bit lines; a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a transistor having a current path provided between a corresponding bit line and one electrode of said capacitor; an amplifier coupled to said pair of bit lines, wherein said amplifier senses voltage levels of said pair of bit lines and supplies a first voltage and a second voltage which is larger than said first voltage to said pair of bit lines; a voltage generating circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage; and a timer circuit which measures a predetermined period after said voltage generating circuit changes from a non-activating state to an activating state, wherein access to said memory cells is inhibited until said predetermined period has expired.