Patent US5960464A successfully refreshed from Google Patents.
US5960464A
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Memory sharing architecture for a decoding in a computer system
Assignee: Parthenon Unified Memory Architecture LLC
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Filing: 1996-08-23
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Granted: 1999-09-28
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Expires: 2016-08-23
Abstract
Abstract A method and apparatus employing a memory management system that can be used with applications requiring a large contiguous block of memory, such as video decompression techniques (e.g., MPEG 2 decoding). The system operates with a computer and the computer's operating system to request and employ approximately 500 4-kilobyte pages in two or more noncontiguous blocks of the main memory to construct a contiguous 2-megabyte block of memory. The system can employ, on a single chip, a direct memory access engine, a microcontroller, a small block of optional memory, and a video decoder circuit. The microcontroller retains the blocks of multiple pages of the main memory, and the page descriptors of these blocks, so as to lock down these blocks of memory and prohibit the operating system or other applications from using them. The microcontroller requests the page descriptors for each of the blocks, and programs a lookup table or memory mapping system in the on-chip memory to form a contiguous block of memory. As a result, the video decoder circuit can perform operations on a 2-megabyte contiguous block of memory, where the microcontroller employs the lookup table to translate each 2-megabyte contiguous address requested by the video decoder circuit to its appropriate page in the main memory. As soon as the video decoding operations are complete, the microcontroller releases the blocks of multiple pages of memory back for use by the computer.
Inventors
- 👤 Christopher S. Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126; H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N19/60; H04N19/61
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
156 words
In a computer system having a main memory, a storage device having encoded data stored therein and a processor controlled by an operating system, an electronic device comprising: a decoding circuit coupled to receive and decode the encoded data from the storage device; and a control circuit coupled to the decoding circuit, the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, and wherein the decoding circuit is configured to request at least some of the contiguous addresses of the block of memory, and wherein the control circuit translates the requested contiguous addresses of the block of memory to requested noncontiguous addresses and permits the decoding circuit to access the portions of the main memory.
Claim 2
Dependent Claim
156 words
In a computer system having a main memory, a storage device having encoded data stored therein and a processor controlled by an operating system, an electronic device comprising: a decoding circuit coupled to receive and decode the encoded data from the storage device; and a control circuit coupled to the decoding circuit, the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, and wherein the decoding circuit is configured to request at least some of the contiguous addresses of the block of memory, and wherein the control circuit translates the requested contiguous addresses of the block of memory to requested noncontiguous addresses and permits the decoding circuit to access the portions of the main memory.
Claim 3
Dependent Claim
17 words
The electronic device of claim 1 wherein the decoding circuit and the control circuit are monolithically integrated.
Claim 4
Dependent Claim
15 words
The electronic device of claim 1 wherein the decoding circuit is a video decoding circuit.
Claim 5
Dependent Claim
15 words
The electronic device of claim 1 wherein the decoding circuit is an audio decoding circuit.
Claim 6
Dependent Claim
25 words
The electronic device of claim 1 wherein the storage device is a DVD player and wherein the decoding circuit is an MPEG 2 decoding circuit.
Claim 7
Dependent Claim
31 words
The electronic device of claim 1 wherein the control circuit includes a memory that stores a look up table, the look up table mapping the noncontiguous addresses to the contiguous addresses.
Claim 8
Dependent Claim
28 words
The electronic device of claim 1 wherein the control circuit includes a memory management unit that is configured to algorithmically translate the noncontiguous addresses to the contiguous addresses.
Claim 9
Dependent Claim
25 words
The electronic device of claim 1 wherein the control circuit includes a direct memory access engine coupled between the main memory and the decoding circuit.
Claim 10
Dependent Claim
35 words
The electronic device of claim 1 wherein the control circuit is further configured to release the portions of the main memory to the operating system when the decoding circuit ceases to request the contiguous addresses.
Claim 11
Dependent Claim
94 words
In a computer system controlled by an operating system and having a main memory, an electronic device comprising: a control circuit coupled to the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the memory portions having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, wherein the control circuit permits access to the portions of the main memory as the block of memory based on the contiguous addresses.
Claim 12
Dependent Claim
94 words
In a computer system controlled by an operating system and having a main memory, an electronic device comprising: a control circuit coupled to the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the memory portions having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, wherein the control circuit permits access to the portions of the main memory as the block of memory based on the contiguous addresses.
Claim 13
Dependent Claim
17 words
The electronic device of claim 10 wherein the main memory and the control circuit are monolithically integrated.
Claim 14
Dependent Claim
17 words
The electronic device of claim 10, further comprising a video decoding circuit coupled to the control circuit.
Claim 15
Dependent Claim
17 words
The electronic device of claim 10, further comprising an audio decoding circuit coupled to the control circuit.
Claim 16
Dependent Claim
21 words
The electronic device of claim 10, further comprising a DVD player and an MPEG2 decoding circuit coupled to the control circuit.
Claim 17
Dependent Claim
31 words
The electronic device of claim 10 wherein the control circuit includes a memory that stores a look up table, the look up table translating the noncontiguous addresses to the contiguous addresses.
Claim 18
Dependent Claim
27 words
The electronic device of claim 10 wherein the control circuit includes a memory management unit that is configured to translate the noncontiguous addresses to the contiguous addresses.
Claim 19
Dependent Claim
21 words
The electronic device of claim 10 wherein the control circuit includes a direct memory access engine coupled to the main memory.
Claim 20
Dependent Claim
37 words
The electronic device of claim 10 wherein the control circuit is further configured to release the portions of the main memory to the operating system when the control circuit receives a termination signal from the computer system.
Claim 21
Dependent Claim
109 words
A computer system, comprising: a main memory; a storage device having encoded data stored therein; a processor coupled to the main memory and the storage device and controlled by an operating system; and a control circuit coupled to the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the memory portions having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, wherein the control circuit permits access to the portions of the main memory through the block of memory based on the contiguous addresses.
Claim 22
Dependent Claim
109 words
A computer system, comprising: a main memory; a storage device having encoded data stored therein; a processor coupled to the main memory and the storage device and controlled by an operating system; and a control circuit coupled to the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the memory portions having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, wherein the control circuit permits access to the portions of the main memory through the block of memory based on the contiguous addresses.
Claim 23
Dependent Claim
17 words
The computer system of claim 19, further comprising a video decoding circuit coupled to the control circuit.
Claim 24
Dependent Claim
17 words
The computer system of claim 19, further comprising an audio decoding circuit coupled to the control circuit.
Claim 25
Dependent Claim
28 words
The computer system of claim 19 wherein the control circuit includes a memory management unit that is configured to algorithmically translate the noncontiguous addresses to the contiguous addresses.
Claim 26
Dependent Claim
21 words
The computer system of claim 19 wherein the control circuit includes a direct memory access engine coupled to the main memory.
Claim 27
Dependent Claim
36 words
The computer system of claim 19 wherein the control circuit is further configured to release the portions of the main memory to the operating system when the control circuit receives a termination signal from the processor.
Claim 28
Dependent Claim
142 words
In a computer system having a processor controlled by an operating system and having a main memory, a storage device having encoded data stored therein, a decoding circuit coupled to receive and decode the encoded data from the storage device, and a control circuit coupled to the decoding circuit, the processor, and the main memory, the control circuit using a memory management method comprising the steps of: requesting contiguous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses; translating the noncontiguous addresses to contiguous addresses of a block of memory; receiving requests for access to a block of memory from the decoding circuit; translating the contiguous addresses to the noncontiguous addresses; and providing access to the portions of the main memory as the block of memory for the decoding circuit.
Claim 29
Dependent Claim
142 words
In a computer system having a processor controlled by an operating system and having a main memory, a storage device having encoded data stored therein, a decoding circuit coupled to receive and decode the encoded data from the storage device, and a control circuit coupled to the decoding circuit, the processor, and the main memory, the control circuit using a memory management method comprising the steps of: requesting contiguous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses; translating the noncontiguous addresses to contiguous addresses of a block of memory; receiving requests for access to a block of memory from the decoding circuit; translating the contiguous addresses to the noncontiguous addresses; and providing access to the portions of the main memory as the block of memory for the decoding circuit.
Claim 30
Dependent Claim
25 words
The method of claim 25 wherein the encoded data is video data, and wherein the method further includes the step of decoding the video data.
Claim 31
Dependent Claim
25 words
The method of claim 25 wherein the encoded data is audio data, and wherein the method further includes the step of decoding the audio data.
Claim 32
Dependent Claim
35 words
The method of claim 25 wherein the storage device is a DVD player that produces video data, and wherein the method further includes the step of decoding the video data under an MPEG2 decoding routine.
Claim 33
Dependent Claim
31 words
The method of claim 25 wherein the step of translating includes the step of forming a look up table, the look up table translating the noncontiguous addresses to the contiguous addresses.
Claim 34
Dependent Claim
39 words
The method of claim 25 wherein the step of providing access to the portions of the main memory includes the step of employing direct memory access instructions to couple the decoding circuit to the portions of the main memory.
Claim 35
Dependent Claim
30 words
The method of claim 25, further comprising the steps of: receiving an instruction to terminate decoding; and releasing the several memory portions of the main memory to the operating system.
Claim 36
Dependent Claim
82 words
In a computer system having a processor controlled by an operating system, having a main memory and a control circuit using a memory management method comprising the steps of: requesting continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses; translating the noncontiguous addresses to contiguous addresses of a block of memory; receiving requests for access to a block of memory; and translating the contiguous addresses to the noncontiguous addresses.
Claim 37
Dependent Claim
82 words
In a computer system having a processor controlled by an operating system, having a main memory and a control circuit using a memory management method comprising the steps of: requesting continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses; translating the noncontiguous addresses to contiguous addresses of a block of memory; receiving requests for access to a block of memory; and translating the contiguous addresses to the noncontiguous addresses.
Claim 38
Dependent Claim
49 words
The method of claim 32 wherein the computer system includes a decoding circuit coupled to the main memory, and wherein the method includes the step of providing access to the portions of the main memory as the block of memory for the decoding circuit based on the contiguous addresses.
Claim 39
Dependent Claim
52 words
The method of claim 32 wherein the computer system includes an MPEG2 video decoding circuit coupled to the main memory, and wherein the method includes the step of providing access to the portions of the main memory as the block of memory for the video decoding circuit based on the contiguous addresses.
Claim 40
Dependent Claim
51 words
The method of claim 32 wherein the computer system includes an audio decoding circuit coupled to the main memory, and wherein the method includes the step of providing access to the portions of the main memory as the block of memory for the audio decoding circuit based on the contiguous addresses.
Claim 41
Dependent Claim
49 words
The method of claim 32 wherein the computer system includes a software application operable under the operating system, and wherein the method includes the step of providing access to the portions of the main memory as the block of memory for the software application based on the contiguous addresses.
Claim 42
Dependent Claim
31 words
The method of claim 32 wherein the step of translating includes the step of forming a look up table, the look up table translating the noncontiguous addresses to the contiguous addresses.
Claim 43
Dependent Claim
60 words
The method of claim 32 wherein the computer system includes a software application operable under the operating system, and wherein the method includes the step of providing access to the portions of the main memory by employing direct memory access instructions to provide access to the portions of the main memory as the block of memory for the software application.
Claim 44
Dependent Claim
60 words
The method of claim 32 wherein the computer system includes a decoding circuit coupled to the main memory, and wherein the method includes the step of providing access to the portions of the main memory by employing direct memory access instructions to provide access to the portions of the main memory as the block of memory for the decoding circuit.
Claim 45
Dependent Claim
28 words
The method of claim 32, further comprising the steps of: receiving a termination instruction; and releasing the several memory portions of the main memory to the operating system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-27 | 2003-03-29 | 2003-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-27 | 2007-03-29 | 2007-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-27 | 2011-03-29 | 2011-09-28 | $7700.00 | Window Closed / Lapsed |