Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
225 words
A digital signal decoder system for receiving compressed encoded digital video signals and transmitting decompressed decoded digital video signals, said decoder system comprising: a. a FIFO Data Buffer; b. a memory having (1) a compressed, encoded Data Buffer connected to the FIFO Data Buffer and adapted to receive and store encoded compressed digital video data from the FIFO Data Buffer, and (2) a data portion for storing decompressed digital video data; c. a Memory Management Unit for managing the RAM; d. a Variable Length Code Decoder for receiving encoded data from the compressed, encoded Data Buffer portion of the RAM, and providing a decoded bit stream thereof; e. an Inverse Quantizer having multiplier circuits constructed of a (2,3,3) parallel counter for dequantizing the decoded data from the variable length decoder; f. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures; g. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM; h. a Display Unit to output motion compensated pictures from the RAM; and i. a Reduced Instruction Set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.
Claim 2
Dependent Claim
27 words
The system of claim 1 having a downstream video element chosen from the group consisting of a digital computer, a television set, a recorder, and a network.
Claim 3
Dependent Claim
12 words
The system of claim 1 or 2 further comprising an audio decoder.
Claim 4
Independent Claim
16 words
The system of one of claims 1 to 3 wherein said system is a stand-alone system.
Claim 5
Dependent Claim
21 words
The system of claim 4 wherein the system is present on one or more printed circuit boards in said downstream element.
Claim 6
Independent Claim
36 words
The system of one of claims 1 to 5 wherein said decoder system is integrated with a downstream element chosen from the group consisting of a digital computer, a television set, a recorder, and a network.
Claim 7
Independent Claim
64 words
The system of one of claims 1 to 6 wherein the (2,3,3) parallel counter has the Boolean representation: C'' = (U NAND V) NAND ((U XOR V) NAND ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z))), C' = (U XOR V) XOR ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and S = (X XOR Y) XOR Z.
Claim 8
Dependent Claim
211 words
An integrated circuit chip for a system for receiving encoded digitized video signals and transmitting decoded digital video signals, said system including the integrated circuit chip and a RAM with (1) a compressed, encoded Data Buffer adapted to receive and store encoded compressed digital video data, and (2) a data portion for storing decompressed digital video buffer, a Memory Management Unit for managing the RAM, the integrated circuit chip comprising: a. a FIFO Data Buffer; b. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof; c. Inverse Quantizer for dequantizing the decoded data from the variable length decoder comprising (2,3,3) parallel counters; d. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures; e. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM; f. a Display Unit to output motion compensated pictures from the RAM; and g. a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.
Claim 9
Dependent Claim
32 words
An Inverse Discrete Cosine Transform video decoder having a variable length decoder, an inverse quantizer, and an inverse discrete cosine transform transformer, the improvement wherein the inverse quantizer comprises (2,3,3) parallel counters.
Claim 10
Dependent Claim
65 words
The Inverse Discrete cosine transform decoder of claim 9 wherein the (2,3,3) parallel counter is represented by the Boolean terms: C'' = (U NAND V) NAND ((U XOR V) NAND ((NAND Y) NAND (X NAND Z) NAND (Y NAND Z))), C' = (U XOR V) XOR ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and S = (X XOR 7) XOR Z.