Process of forming titanium silicide interconnects

Claim 2

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a patterned structure over said at least one semiconductor layer, said patterned structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium suicide such that a layer of titanium nitride and said titanium silicide interconnect structure are formed.

Claim 3

The process of claim 1, wherein said layer of titanium nitride has a thickness in the range of about 50 Angstroms to about 200 Angstroms.

Claim 4

The process of claim 2, wherein said layer of titanium nitride has a thickness of approximately 150 Angstroms.

Claim 5

The process of claim 1, wherein nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride is formed comprises nitrifying substantially all of the exposed portions of said layer of titanium silicide such that said layer of titanium nitride is formed on substantially all of said exposed portions of said layer of titanium silicide.

Claim 6

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a patterned structure over said at least one semiconductor layer, said patterned structure comprising a layer of polysilicon, a layer of titanium silicide, and a layer of insulating material; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and said titanium silicide interconnect structure are formed.

Claim 7

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a patterned structure over said at least one semiconductor layer, said patterned structure comprising a layer of polysilicon, a layer of titanium silicide, and a layer of insulating material; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and said titanium silicide interconnect structure are formed.

Claim 8

The process of claim 5, wherein said layer of titanium silicide is positioned between said layer of polysilicon and said layer of insulating material such that said layer of titanium silicide comprises at least one exposed side, and wherein nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride is formed comprises nitrifying said at least one exposed side of said layer of titanium silicide such that a layer of titanium nitride is formed on said at least one exposed side of said layer of titanium silicide.

Claim 9

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a patterned structure over said at least one semiconductor layer, said patterned structure comprising a layer of polysilicon and a layer of titanium silicide; annealing said layer of titanium silicide in the presence of a composition having a reactive nitrogen to convert a portion of said titanium silicide to a layer of titanium nitride and thereby form said titanium silicide interconnect structure, said layer of titanium nitride having a thickness in the range of about 50 Angstroms to about 200 Angstroms.

Claim 10

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a patterned structure over said at least one semiconductor layer, said patterned structure comprising a layer of polysilicon and a layer of titanium silicide; annealing said layer of titanium silicide in the presence of a composition having a reactive nitrogen to convert a portion of said titanium silicide to a layer of titanium nitride and thereby form said titanium silicide interconnect structure, said layer of titanium nitride having a thickness in the range of about 50 Angstroms to about 200 Angstroms.

Claim 11

The process of claim 7, wherein annealing said layer of titanium silicide is carried out at a temperature ranging from about 500° C. to about 800° C.

Claim 12

The process of claim 7, wherein said composition having a reactive nitrogen is selected from the group consisting of NH 3 , N 2 H 4 and a plasma of N 2 gas.

Claim 13

The process of claim 7, wherein said patterned structure further comprises a layer of insulating material on said layer of titanium silicide.

Claim 14

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer, said layer of polysilicon having a thickness in the range of about 500 Angstroms to about 1500 Angstroms; forming a layer of titanium silicide over said layer of polysilicon, said layer of titanium silicide having a thickness in the range of about 1000 Angstroms to about 2000 Angstroms; patterning said layer of titanium silicide and said layer of polysilicon; and forming a layer of titanium nitride on a portion of said layer of titanium silicide by annealing said layer of titanium silicide in the presence of a composition having a reactive nitrogen to thereby form said titanium silicide interconnect structure, said layer of titanium nitride having a thickness in the range of about 50 Angstroms to about 200 Angstroms.

Claim 15

A process of forming a titanium silicide interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer, said layer of polysilicon having a thickness in the range of about 500 Angstroms to about 1500 Angstroms; forming a layer of titanium silicide over said layer of polysilicon, said layer of titanium silicide having a thickness in the range of about 1000 Angstroms to about 2000 Angstroms; patterning said layer of titanium silicide and said layer of polysilicon; and forming a layer of titanium nitride on a portion of said layer of titanium silicide by annealing said layer of titanium silicide in the presence of a composition having a reactive nitrogen to thereby form said titanium silicide interconnect structure, said layer of titanium nitride having a thickness in the range of about 50 Angstroms to about 200 Angstroms.

Claim 16

A process of forming a field effect transistor having a self-aligned gate, said process comprising: providing a substrate assembly having at least one semiconductor layer; forming a source, a drain and said self-aligned gate of said field effect transistor in said at least one semiconductor layer; forming a patterned interconnect structure for said self-aligned gate, said patterned interconnect structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide interconnect structure are formed.

Claim 17

A process of forming a field effect transistor having a self-aligned gate, said process comprising: providing a substrate assembly having at least one semiconductor layer; forming a source, a drain and said self-aligned gate of said field effect transistor in said at least one semiconductor layer; forming a patterned interconnect structure for said self-aligned gate, said patterned interconnect structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide interconnect structure are formed.

Claim 18

A process of forming a memory array, said memory array comprising a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells comprising at least one field effect transistor, said process comprising: providing at least one semiconductor layer; forming sources, drains and gates for each of said field effect transistors over said at least one semiconductor layer; forming a patterned structure for interconnecting desired gates of each of said field effect transistors and other structures formed as part of said memory array, said patterned structure comprising a layer of polysilicon and a layer of titanium suicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide interconnect structure are formed.

Claim 19

A process of forming a memory array, said memory array comprising a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells comprising at least one field effect transistor, said process comprising: providing at least one semiconductor layer; forming sources, drains and gates for each of said field effect transistors over said at least one semiconductor layer; forming a patterned structure for interconnecting desired gates of each of said field effect transistors and other structures formed as part of said memory array, said patterned structure comprising a layer of polysilicon and a layer of titanium suicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide interconnect structure are formed.

Claim 20

A process of fabricating a wafer comprising: providing a wafer having a substrate assembly, said substrate assembly having at least one semiconductor layer; forming a repeating series of sources, drains and gates for at least one field effect transistor on each of a plurality of individual die on said wafer over said at least one semiconductor layer; forming a patterned interconnect structure for each of said field effect transistors on each of said plurality of individual die on said wafer, said patterned interconnect structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide interconnect structure are formed.

Claim 21

A process of fabricating a wafer comprising: providing a wafer having a substrate assembly, said substrate assembly having at least one semiconductor layer; forming a repeating series of sources, drains and gates for at least one field effect transistor on each of a plurality of individual die on said wafer over said at least one semiconductor layer; forming a patterned interconnect structure for each of said field effect transistors on each of said plurality of individual die on said wafer, said patterned interconnect structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide interconnect structure are formed.

Claim 22

The process of claim 1, wherein said layer of polysilicon has a thickness in the range of about 500 Angstroms to about 1500 Angstroms.

Claim 23

The process of claim 15, said layer of titanium silicide has a thickness in the range of about 1000 Angstroms to about 2000 Angstroms.

Claim 24

A process of forming a titanium silicide structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of titanium silicide over said layer of polysilicon; patterning said layer of titanium silicide and said layer of polysilicon; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride is formed.

Claim 25

A process of forming a titanium silicide structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of titanium silicide over said layer of polysilicon; patterning said layer of titanium silicide and said layer of polysilicon; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride is formed.

Claim 26

The process of claim 17, wherein said layer of titanium nitride has a thickness in the range of about 50 Angstroms to about 200 Angstroms.

Claim 27

The process of claim 18, wherein said layer of titanium nitride has a thickness of approximately 150 Angstroms.

Claim 28

The process of claim 15, wherein nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride is formed comprises nitrifying substantially all of the exposed portions of said layer of titanium silicide such that said layer of titanium nitride is formed on substantially all of said exposed portions of said layer of titanium silicide.

Claim 29

The process of claim 15, wherein said layer of polysilicon has a thickness in the range of about 500 Angstroms to about 1500 Angstroms.

Claim 30

The process of claim 21, wherein said layer of titanium silicide has a thickness in the range of about 1000 Angstroms to about 2000 Angstroms.

Claim 31

A process of forming a gate structure for a field effect transistor having a self-aligned gate, said process comprising: providing a substrate assembly having at least one semiconductor layer; forming a source and a drain of said field effect transistor in said at least one semiconductor layer; forming a patterned structure for said self-aligned gate, said patterned structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide gate structure are formed.

Claim 32

A process of forming a gate structure for a field effect transistor having a self-aligned gate, said process comprising: providing a substrate assembly having at least one semiconductor layer; forming a source and a drain of said field effect transistor in said at least one semiconductor layer; forming a patterned structure for said self-aligned gate, said patterned structure comprising a layer of polysilicon and a layer of titanium silicide; and nitrifying a portion of said layer of titanium silicide such that a layer of titanium nitride and a titanium silicide gate structure are formed.