Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device

Claim 1

A method of simultaneously fabricating a capacitor plate, for a stacked capacitor structure, a word line contact structure, and a metal contact structure, for a DRAM device, comprising the steps of: providing transfer gate transistors, on a semiconductor substrate, comprised of polycide gate structures, on a gate insulator layer, with source and drain regions in said semiconductor substrate, in an area not covered by said polycide gate structures; providing a polysilicon contact plug, in contact hole in a first insulator layer, with the polysilicon contact plug placed between said polysilicon gate structures of said transfer gate transistor, and with said polysilicon contact plug, contacting a source and drain region, of said transfer gate transistor; opening a storage node contact hole, in a first composite insulator layer, exposing the top surface of said polysilicon contact plug; forming a storage node electrode, in said storage node contact hole, contacting said polysilicon contact plug; forming a capacitor dielectric layer on said storage node electrode; opening a metal contact hole in a second composite insulator layer, exposing a region of said semiconductor substrate; opening a word line contact hole in a third composite insulator layer, exposing the top surface of a polycide gate structure; depositing a barrier layer on said capacitor dielectric layer, overlying said storage node electrode, and coating the sides of, and the bottom of, said metal contact hole, and the sides of, and the bottom of, said word line contact hole; depositing a tungsten layer on said barrier layer, completely filling said metal contact hole and said word line contact hole; and patterning of said tungsten layer, and of said barrier layer, to create said capacitor plate, on said capacitor dielectric layer of said storage node electrode, and to create said word line contact structure, in said word line contact hole, and said metal contact structure, in said metal contact hole.

Claim 2

A method of simultaneously fabricating a capacitor plate, for a stacked capacitor structure, a word line contact structure, and a metal contact structure, for a DRAM device, comprising the steps of: providing transfer gate transistors, on a semiconductor substrate, comprised of polycide gate structures, on a gate insulator layer, with source and drain regions in said semiconductor substrate, in an area not covered by said polycide gate structures; providing a polysilicon contact plug, in contact hole in a first insulator layer, with the polysilicon contact plug placed between said polysilicon gate structures of said transfer gate transistor, and with said polysilicon contact plug, contacting a source and drain region, of said transfer gate transistor; opening a storage node contact hole, in a first composite insulator layer, exposing the top surface of said polysilicon contact plug; forming a storage node electrode, in said storage node contact hole, contacting said polysilicon contact plug; forming a capacitor dielectric layer on said storage node electrode; opening a metal contact hole in a second composite insulator layer, exposing a region of said semiconductor substrate; opening a word line contact hole in a third composite insulator layer, exposing the top surface of a polycide gate structure; depositing a barrier layer on said capacitor dielectric layer, overlying said storage node electrode, and coating the sides of, and the bottom of, said metal contact hole, and the sides of, and the bottom of, said word line contact hole; depositing a tungsten layer on said barrier layer, completely filling said metal contact hole and said word line contact hole; and patterning of said tungsten layer, and of said barrier layer, to create said capacitor plate, on said capacitor dielectric layer of said storage node electrode, and to create said word line contact structure, in said word line contact hole, and said metal contact structure, in said metal contact hole.

Claim 14

A method of fabricating a DRAM device, on a semiconductor substrate, in which a capacitor plate of a stacked capacitor structure, a word line contact structure, and a metal contact structure, are formed using a single deposition procedure, and a single patterning procedure, comprising the steps of: providing transfer gate transistors, on said semiconductor substrate, comprised of silicon nitride encapsulated, polycide gate structures, on a silicon dioxide gate insulator layer, and with source and drain regions, in said semiconductor substrate, between said silicon nitride encapsulated, polycide gate structures; depositing a first insulator layer; planarizing said first insulator layer; forming self-aligned contact holes, in said first insulator layer, to a first source and drain region, and to a second source and drain region; depositing a first polysilicon layer, completely filling said self-aligned contact holes; removing said first polysilicon layer from the top surface of said first insulator layer, resulting in the formation of polysilicon contact plugs, in said self-aligned contact holes; recessing of said polysilicon contact plugs, in said self-aligned contact holes, to a level below the top surface of said first insulator layer; depositing a second insulator layer; opening bit line contact holes to a first polysilicon contact plug, overlying a first source and drain region; depositing a second polysilicon layer; depositing a tungsten silicide layer; patterning of said tungsten silicide layer, and of said second polysilicon layer, to create a bit line contact structure, in said bit line contact hole, overlying said first polysilicon contact plug; depositing a third insulator layer; planarizing said third insulator layer; opening a storage node contact hole in said third insulator layer, and in said second insulator layer, exposing the top surface of a second polysilicon contact plug, overlying said second source and drain region; depositing a third polysilicon layer; patterning of said third polysilicon layer to create a storage node electrode, in said storage node contact hole; forming a capacitor dielectric layer on said storage node contact hole; opening a metal contact hole in said third insulator layer, in said second insulator layer, and in said first insulator layer, exposing a region of said semiconductor substrate; opening a word line contact hole in said third insulator layer, in said second insulator layer, in said first insulator layer, and in said silicon nitride encapsulated layer, exposing the top surface of said polycide gate structure; depositing a barrier layer on said capacitor dielectric layer, on said storage node electrode, and on exposed surfaces of said metal contact hole, and on exposed surfaces of said word line contact hole; depositing a tungsten layer on said barrier layer, completely filling said metal contact hole, and completely filling said word line contact hole; and patterning of said tungsten layer, and of said barrier layer, to simultaneously form capacitor plate, for said stacked capacitor structure, said metal contact structure in said metal contact hole, and said word line contact structure, in said word line contact hole.

Claim 15

A method of fabricating a DRAM device, on a semiconductor substrate, in which a capacitor plate of a stacked capacitor structure, a word line contact structure, and a metal contact structure, are formed using a single deposition procedure, and a single patterning procedure, comprising the steps of: providing transfer gate transistors, on said semiconductor substrate, comprised of silicon nitride encapsulated, polycide gate structures, on a silicon dioxide gate insulator layer, and with source and drain regions, in said semiconductor substrate, between said silicon nitride encapsulated, polycide gate structures; depositing a first insulator layer; planarizing said first insulator layer; forming self-aligned contact holes, in said first insulator layer, to a first source and drain region, and to a second source and drain region; depositing a first polysilicon layer, completely filling said self-aligned contact holes; removing said first polysilicon layer from the top surface of said first insulator layer, resulting in the formation of polysilicon contact plugs, in said self-aligned contact holes; recessing of said polysilicon contact plugs, in said self-aligned contact holes, to a level below the top surface of said first insulator layer; depositing a second insulator layer; opening bit line contact holes to a first polysilicon contact plug, overlying a first source and drain region; depositing a second polysilicon layer; depositing a tungsten silicide layer; patterning of said tungsten silicide layer, and of said second polysilicon layer, to create a bit line contact structure, in said bit line contact hole, overlying said first polysilicon contact plug; depositing a third insulator layer; planarizing said third insulator layer; opening a storage node contact hole in said third insulator layer, and in said second insulator layer, exposing the top surface of a second polysilicon contact plug, overlying said second source and drain region; depositing a third polysilicon layer; patterning of said third polysilicon layer to create a storage node electrode, in said storage node contact hole; forming a capacitor dielectric layer on said storage node contact hole; opening a metal contact hole in said third insulator layer, in said second insulator layer, and in said first insulator layer, exposing a region of said semiconductor substrate; opening a word line contact hole in said third insulator layer, in said second insulator layer, in said first insulator layer, and in said silicon nitride encapsulated layer, exposing the top surface of said polycide gate structure; depositing a barrier layer on said capacitor dielectric layer, on said storage node electrode, and on exposed surfaces of said metal contact hole, and on exposed surfaces of said word line contact hole; depositing a tungsten layer on said barrier layer, completely filling said metal contact hole, and completely filling said word line contact hole; and patterning of said tungsten layer, and of said barrier layer, to simultaneously form capacitor plate, for said stacked capacitor structure, said metal contact structure in said metal contact hole, and said word line contact structure, in said word line contact hole.