US5953611A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating nonvolatile semiconductor memory devices with select gates
Assignee: Ricoh Co Ltd
•
Filing: 1997-05-30
•
Granted: 1999-09-14
•
Expires: 2017-05-30
Abstract
Abstract A method of producing a nonvolatile semiconductor memory devices in which a source line is formed in a self-alignment fashion, wherein the nonvolatile semiconductor tunnel oxide film, a control gate electrode formed on the floating gate electrode, and a select gate electrode formed on the control gate electrode, and a part of the select gate electrode is disposed on the channel via a gate dielectric layer. The method includes the steps of: forming a side wall film, which will be used in self-alignment processing, on a side of the multilayer structure consisting of the floating gate electrode and the control gate electrode; implanting impurity ions into a region intended to become a source line in a self-alignment fashion using the side wall film as a mask thereby forming the source line; and forming the select gate electrode while keeping at least the portion of the film in the space above the drain line remaining without being removed.
Inventors
- 👤 Makoto Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:55
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
220 words
A method of producing a nonvolatile semiconductor memory, comprising: forming stacked gate structures on a semiconductor substrate defining source and drain line regions relative to said stacked gate structures, wherein said source and drain line regions are parallel to said stacked gate structures, and wherein at least said source line region is spaced from said stacked gate structure by a sub-channel region and said drain line region is adjacent said stacked gate structure, a distance between said stacked gate structure and said source line region defined as a split gate length; forming a side wall film on a side of each of said stacked gate structures; filling regions adjacent said drain line regions with a material that is the same as a material used to form said side wall films; implanting impurity ions in said source line regions in a self-alignment fashion using said side wall films and said filled regions as masks so as to form source lines the split gate length being defined by a width of said side wall films; and forming line shaped select gate electrodes on top and side surfaces of said stacked gate structures via insulating films and on said sub-channel regions of said substrate via gate oxide films, wherein said select gate electrodes are formed without removing said material in said filled regions.
Claim 2
Independent Claim
220 words
A method of producing a nonvolatile semiconductor memory, comprising: forming stacked gate structures on a semiconductor substrate defining source and drain line regions relative to said stacked gate structures, wherein said source and drain line regions are parallel to said stacked gate structures, and wherein at least said source line region is spaced from said stacked gate structure by a sub-channel region and said drain line region is adjacent said stacked gate structure, a distance between said stacked gate structure and said source line region defined as a split gate length; forming a side wall film on a side of each of said stacked gate structures; filling regions adjacent said drain line regions with a material that is the same as a material used to form said side wall films; implanting impurity ions in said source line regions in a self-alignment fashion using said side wall films and said filled regions as masks so as to form source lines the split gate length being defined by a width of said side wall films; and forming line shaped select gate electrodes on top and side surfaces of said stacked gate structures via insulating films and on said sub-channel regions of said substrate via gate oxide films, wherein said select gate electrodes are formed without removing said material in said filled regions.
Claim 3
Dependent Claim
20 words
The method according to claim 1, wherein said side wall films are formed on said sub-channel regions of said substrate.
Claim 4
Dependent Claim
21 words
The method according to claim 1, wherein said side wall films and said filled regions are formed of oxide and/or nitride.
Claim 5
Dependent Claim
19 words
The method according to claim 1, wherein said side wall films and said filled regions are formed of polysilicon.
Claim 6
Dependent Claim
26 words
The method according to claim 1, said side wall films and said filled regions are used as a portion of each of said select gate electrodes.
Claim 7
Dependent Claim
53 words
The method according to claim 1, wherein a polysilicon layer having a thickness of about 10 to 30 mm is formed on each of said side wall films and said filled regions, and a high melting point metal layer or a high melting point metal silicide layer is formed on said polysilicon layer.
Claim 8
Dependent Claim
49 words
The method according to claim 6, wherein said side wall films are formed of polysilicon, and wherein said side wall films or said polysilicon layers and/or high melting point metal layers or high melting point metal silicide layers are used to form a gate electrode of a peripheral circuit.
Claim 9
Dependent Claim
67 words
The method according to claim 7, wherein when the polysilicon layer of said side wall films are used to form the gate electrode of a peripheral circuit, an two step etching-back processing is performed in such a manner that a photolithography process is performed between each etching-back step so as to reduce a slope and/or height of geographical steps of the gate electrode of the peripheral circuit.
Claim 10
Dependent Claim
26 words
The method according to claim 1, wherein oxidation is performed after forming said select gate electrodes and before forming the gate electrode of a peripheral circuit.
References Cited (Backward Citations)
US4203158A
Cited
US4203158B1
Cited
US4698787A
Cited
US4868619A
Cited
US4852062A
Cited
US5198380A
Cited
US5070032A
Cited
US5229631A
Cited
US5280446A
Cited
US5268585A
Cited
US5429969A
Cited
JPH0852915A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |