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US5952039A
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Method for manufacturing DRAM capacitor
Assignee: United Microelectronics Corp
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Filing: 1998-01-20
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Granted: 1999-09-14
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Expires: 2018-01-20
Abstract
Abstract A method for manufacturing DRAM capacitor that utilizes a self-aligned operation to form a forked-shaped capacitor structure having dual trenches or a multiple of trenches. No additional masking steps are required, and the uneven surface produced by the method of this invention is able to increase the surface area of the lower electrode. Hence, a high capacitance for the DRAM capacitor is obtained and a high level integration of DRAM cells can be realized.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
271 words
A method for manufacturing a DRAM capacitor on a semiconductor substrate, wherein one or more MOS transistors is formed on the substrate, with one source/drain terminal of a MOS transistor electrically coupled to a bit line, comprising the steps of: forming an insulating layer and a silicon nitride layer over the substrate; patterning the silicon nitride layer and the insulating layer to form a via exposing the bit line; forming a first polysilicon layer and a first oxide layer over the silicon nitride layer, wherein the first polysilicon layer also completely fills the via; patterning the first oxide layer, and then forming silicon nitride spacers on the sidewalls of the patterned first oxide layer covering a portion of the first polysilicon layer; forming a second oxide layer on the exposed first polysilicon layer; removing the silicon nitride spacers, and then using the first oxide layer and the second oxide layer as masks, etching the first polysilicon layer to form two trenches; removing the first oxide layer and the second oxide layer; patterning the first polysilicon layer to form a dual trench structure; removing the silicon nitride layer to expose the insulating layer; forming a hemispherical (rained silicon layer over the insulating layer and the dual trench structure; patterning the hemispherical grained silicon layer using the dual trench structure as a mask, wherein the hemispherical grained silicon layer and the dual trench structure together constitutes a lower electrode of the capacitor after the patterning operation; and forming a dielectric layer and a second polysilicon layer over the lower electrode, wherein the second polysilicon layer acts as an upper electrode for the capacitor.
Claim 2
Independent Claim
271 words
A method for manufacturing a DRAM capacitor on a semiconductor substrate, wherein one or more MOS transistors is formed on the substrate, with one source/drain terminal of a MOS transistor electrically coupled to a bit line, comprising the steps of: forming an insulating layer and a silicon nitride layer over the substrate; patterning the silicon nitride layer and the insulating layer to form a via exposing the bit line; forming a first polysilicon layer and a first oxide layer over the silicon nitride layer, wherein the first polysilicon layer also completely fills the via; patterning the first oxide layer, and then forming silicon nitride spacers on the sidewalls of the patterned first oxide layer covering a portion of the first polysilicon layer; forming a second oxide layer on the exposed first polysilicon layer; removing the silicon nitride spacers, and then using the first oxide layer and the second oxide layer as masks, etching the first polysilicon layer to form two trenches; removing the first oxide layer and the second oxide layer; patterning the first polysilicon layer to form a dual trench structure; removing the silicon nitride layer to expose the insulating layer; forming a hemispherical (rained silicon layer over the insulating layer and the dual trench structure; patterning the hemispherical grained silicon layer using the dual trench structure as a mask, wherein the hemispherical grained silicon layer and the dual trench structure together constitutes a lower electrode of the capacitor after the patterning operation; and forming a dielectric layer and a second polysilicon layer over the lower electrode, wherein the second polysilicon layer acts as an upper electrode for the capacitor.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the step of forming the first oxide layer includes a thermal oxidation method.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein the first oxide layer has a thickness of about 200 Å to 1000 Å.
Claim 5
Dependent Claim
42 words
The method of claim 1, wherein the step of forming the silicon nitride spacers includes the substeps of: forming a silicon nitride layer over the patterned second oxide layer; and etching back the silicon nitride layer to form the silicon nitride spacers.
Claim 6
Dependent Claim
21 words
The method of claim 1, wherein the hemispherical grained silicon layer has a thickness of about 300 Å to 1000 Å.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein the step of removing the silicon nitride layer includes a wet etching method.
Claim 8
Dependent Claim
20 words
The method of claim 6, wherein the step of removing the silicon nitride layer includes using hot phosphoric acid solution.
Claim 9
Dependent Claim
20 words
The method of claim 1, wherein the step of patterning the hemispherical grained silicon layer includes a self-aligned etching operation.
Claim 10
Dependent Claim
27 words
The method of claim 1, wherein the step of forming the dielectric layer includes depositing nitride and oxide (NO) or tantalum oxide (Ta 2 O 5 ).
Claim 11
Independent Claim
274 words
A method for manufacturing a DRAM capacitor on a semiconductor substrate, wherein one or more MOS transistors is formed on the substrate, with one source/drain terminal of a MOS transistor electrically coupled to a bit line, comprising the steps of: forming an insulating layer and a silicon nitride layer over the substrate; patterning the silicon nitride layer and the insulating layer to form a via exposing the bit line; forming a first polysilicon layer and a first oxide layer over the silicon nitride layer, wherein the first polysilicon layer also completely fills the via; patterning the first oxide layer, and then forming silicon nitride spacers on the sidewalls of the patterned first oxide layer covering a portion of the first polysilicon layer; forming a second oxide layer on the exposed first polysilicon layer; removing the silicon nitride spacers, and then using the first oxide layer and the second oxide layer as masks, etching the first polysilicon layer to form a plurality of trenches; removing the first oxide layer and the second oxide layer; patterning the first polysilicon layer to form a fork-shaped structure having a plurality of trenches; removing the silicon nitride layer to expose the insulating layer; forming a hemispherical grained silicon layer over the insulating layer and the fork-shaped structure; patterning the hemispherical grained silicon layer using the fork-shaped structure as a mask, wherein the hemispherical grained silicon layer and the fork-shaped structure together constitute a lower electrode of the capacitor after the patterning operation; and forming a dielectric layer and a second polysilicon layer over the lower electrode, wherein the second polysilicon layer acts as an upper electrode for the capacitor.
Claim 12
Independent Claim
274 words
A method for manufacturing a DRAM capacitor on a semiconductor substrate, wherein one or more MOS transistors is formed on the substrate, with one source/drain terminal of a MOS transistor electrically coupled to a bit line, comprising the steps of: forming an insulating layer and a silicon nitride layer over the substrate; patterning the silicon nitride layer and the insulating layer to form a via exposing the bit line; forming a first polysilicon layer and a first oxide layer over the silicon nitride layer, wherein the first polysilicon layer also completely fills the via; patterning the first oxide layer, and then forming silicon nitride spacers on the sidewalls of the patterned first oxide layer covering a portion of the first polysilicon layer; forming a second oxide layer on the exposed first polysilicon layer; removing the silicon nitride spacers, and then using the first oxide layer and the second oxide layer as masks, etching the first polysilicon layer to form a plurality of trenches; removing the first oxide layer and the second oxide layer; patterning the first polysilicon layer to form a fork-shaped structure having a plurality of trenches; removing the silicon nitride layer to expose the insulating layer; forming a hemispherical grained silicon layer over the insulating layer and the fork-shaped structure; patterning the hemispherical grained silicon layer using the fork-shaped structure as a mask, wherein the hemispherical grained silicon layer and the fork-shaped structure together constitute a lower electrode of the capacitor after the patterning operation; and forming a dielectric layer and a second polysilicon layer over the lower electrode, wherein the second polysilicon layer acts as an upper electrode for the capacitor.
Claim 13
Dependent Claim
19 words
The method of claim 10, wherein the step of forming the first oxide layer includes a thermal oxidation method.
Claim 14
Dependent Claim
42 words
The method of claim 10, wherein the step of forming the silicon nitride spacers includes the substeps of: forming a silicon nitride layer over the patterned second oxide layer; and etching back the silicon nitride layer to form the silicon nitride spacers.
Claim 15
Dependent Claim
19 words
The method of claim 10, wherein the step of removing the silicon nitride layer includes a wet etching method.
Claim 16
Dependent Claim
20 words
The method of claim 13, wherein the step of removing the silicon nitride layer includes using hot phosphoric acid solution.
Claim 17
Dependent Claim
20 words
The method of claim 10, wherein the step of patterning the hemispherical grained silicon layer includes a self-aligned etching operation.
Claim 18
Dependent Claim
27 words
The method of claim 10, wherein the step of forming the dielectric layer includes depositing nitride and oxide (NO) or tantalum oxide (Ta 2 O 5 ).
References Cited (Backward Citations)
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