US5950093A
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Method for aligning shallow trench isolation
Assignee: United Microelectronics Corp
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Filing: 1998-12-30
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Granted: 1999-09-07
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Expires: 2018-12-30
Abstract
Abstract A method for aliging a shallow trench isolation is provided. An aligning mark which is deeper than a prior technique is formed in a provided substrate. A trench is formed and an aligning trench is formed in the position over the aligning mark. A thick oxide layer is deposited on the semiconiductol substrate, in the trench and in the aligning trench. After a portion of the thick oxide layer removed, another portion of the thick oxide layer is removed by etching back. A gate oxide layer is formed on a substrate comprising the trench and the aligning trench. A polysilicon layer with the step-height profile in the position over the aligning mark is formed on the gate oxide layer.
Inventors
- 👤 Chi-Hung Wei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:22
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/0145; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/102; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
208 words
A method for aligning a shallow trench isolation, comprising the steps of: providing a semiconductor substrate; forming a deep alignment mark in the semiconductor substrate; forming a pad oxide layer and a silicon nitride layer on the semiconductor substrate; removing the silicon nitride layer, the pad oxide layer and the semiconductor substrate partially to form a trench in the semiconductor substrate and to form a aligning trench within the aligning mark, wherein the aligning mark and the aligning trench compose a T-shape structure; forming side-wall oxide layers on a side-wall of the trench and on a side-wall of the aligning trench; forming a thick oxide layer on the silicon nitride layer and on the side-wall oxide layers; performing a planarization to remove a portion of the thick oxide layer; removing the thick oxide layer remained on the silicon nitride layer to form a first oxide plug in the trench and to form a second oxide plug in the aligning trench, wherein a top surface of the second oxide plug is lower than a top surface of the semiconductor substrate; removing the silicon nitride layer and the pad oxide layer; forming a gate oxide layer on the semiconductor substrate; and forming a polysilicon layer on the gate oxide layer.
Claim 2
Independent Claim
208 words
A method for aligning a shallow trench isolation, comprising the steps of: providing a semiconductor substrate; forming a deep alignment mark in the semiconductor substrate; forming a pad oxide layer and a silicon nitride layer on the semiconductor substrate; removing the silicon nitride layer, the pad oxide layer and the semiconductor substrate partially to form a trench in the semiconductor substrate and to form a aligning trench within the aligning mark, wherein the aligning mark and the aligning trench compose a T-shape structure; forming side-wall oxide layers on a side-wall of the trench and on a side-wall of the aligning trench; forming a thick oxide layer on the silicon nitride layer and on the side-wall oxide layers; performing a planarization to remove a portion of the thick oxide layer; removing the thick oxide layer remained on the silicon nitride layer to form a first oxide plug in the trench and to form a second oxide plug in the aligning trench, wherein a top surface of the second oxide plug is lower than a top surface of the semiconductor substrate; removing the silicon nitride layer and the pad oxide layer; forming a gate oxide layer on the semiconductor substrate; and forming a polysilicon layer on the gate oxide layer.
Claim 3
Dependent Claim
17 words
The method according to claim 1 wherein the aligning mark has a depth of about 2400 Å.
Claim 4
Dependent Claim
17 words
The method according to claim 1, wherein the aligning, trench has a depth of about 4000 Å.
Claim 5
Dependent Claim
18 words
The method according to claim 1, wherein the side-wall oxide layers have a thickness of about 300 Å.
Claim 6
Dependent Claim
18 words
The method according to claim 1, wherein the thick oxide layer has a thickness of about 7000 Å.
Claim 7
Dependent Claim
14 words
The method according to claim 1, wherein said planarization process comprises a CMP process.
Claim 8
Dependent Claim
18 words
The method according to claim 1, wherein the gate oxide layer has a thickness of about 60 Å.
Claim 9
Dependent Claim
17 words
The method according to claim 1, wherein the polysilicon layer has a thickness of about 3000 Å.
Claim 10
Independent Claim
111 words
A method for aligning a shallow trench isolation, comprising the steps of: providing a semiconductor substrate comprising an aligning mark with a substantially deep step height; forming a trench in the semiconductor substrate and a aligning trench in the position under the aligning mark, wherein the aligning mark and the aligning trench compose a T-shape structure; forming side-wall oxide layers on a side-wall of the trench and on a side-wall of the aligning trench; and forming a first oxide plug in the trench and a second oxide plug in the aligning trench, wherein a top surface of the second oxide plug is lower than a top surface of the semiconductor substrate.
Claim 11
Independent Claim
111 words
A method for aligning a shallow trench isolation, comprising the steps of: providing a semiconductor substrate comprising an aligning mark with a substantially deep step height; forming a trench in the semiconductor substrate and a aligning trench in the position under the aligning mark, wherein the aligning mark and the aligning trench compose a T-shape structure; forming side-wall oxide layers on a side-wall of the trench and on a side-wall of the aligning trench; and forming a first oxide plug in the trench and a second oxide plug in the aligning trench, wherein a top surface of the second oxide plug is lower than a top surface of the semiconductor substrate.
Claim 12
Dependent Claim
43 words
The method according to claim 9, wherein the method further comprises steps after forming the first plug and the second plug, the step comprising: forming a gate oxide layer on the semiconductor substrate; and forming a polysilicon layer on the gate oxide layer.
Claim 13
Dependent Claim
17 words
The method according to claim 9, wherein the aligning mark has a depth of about 2400 Å.
Claim 14
Dependent Claim
17 words
The method according to claim 9, wherein the aligning trench has a depth of about 4000 Å.
Claim 15
Dependent Claim
18 words
The method according to claim 9, wherein the side-wall oxide layers have a thickness of about 300 Å.
Claim 16
Dependent Claim
18 words
The method according to claim 9, wherein the second oxide plug has a thickness of about 5000 Å.
Claim 17
Dependent Claim
18 words
The method according to claim 9, wherein the gate oxide layer has a thickness of about 60 Å.
Claim 18
Dependent Claim
17 words
The method according to claim 9, wherein the polysilicon layer has a thickness of about 3000 Å.
Claim 19
Independent Claim
83 words
A method for aligning a shallow trench isolation, comprising the steps of: providing a semiconductor substrate comprising a alignment mark; forming trench in the semiconductor substrate and an aligning trench at the aligning mark, wherein the aligning mark and the aligning trench compose a T-shape structure; and forming a first oxide plug in the trench and a second oxide plug in the aligning trench, wherein a top surface of the second oxide plug is lower than a top surface of the semiconductor substrate.
Claim 20
Independent Claim
83 words
A method for aligning a shallow trench isolation, comprising the steps of: providing a semiconductor substrate comprising a alignment mark; forming trench in the semiconductor substrate and an aligning trench at the aligning mark, wherein the aligning mark and the aligning trench compose a T-shape structure; and forming a first oxide plug in the trench and a second oxide plug in the aligning trench, wherein a top surface of the second oxide plug is lower than a top surface of the semiconductor substrate.
Claim 21
Dependent Claim
17 words
The method according to claim 17, wherein the aligning mark has a depth of about 2400 Å.
Claim 22
Dependent Claim
17 words
The method according to claim 17, wherein the aligning trench has a depth of about 4000 Å.
Claim 23
Dependent Claim
18 words
The method according to claim 17, wherein the second oxide plug has a thickness of about 5000 Å.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |