US5893744A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench isolation
Assignee: Advanced Micro Devices Inc
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Filing: 1997-01-28
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Granted: 1999-04-13
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Expires: 2017-01-28
Abstract
Abstract A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.
Inventors
- 👤 Larry Yu Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:10
CPC Classifications
H; H10; H10W; H10W46/00; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10W46/501; Y; Y10; Y10S; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
119 words
A method for forming an alignment mark and an isolation trench on a common wafer, the method comprising the steps of: growing a layer of oxide on a semiconductor substrate; depositing a nitride layer on top of the oxide; masking the wafer with a mask having an exposed alignment mark area; etching the nitride layer, the oxide and the substrate through the exposed alignment mark area to form the alignment mark; and forming an isolation trench in the wafer including the steps of masking the wafer to expose the area of the isolation trench and masking the alignment mark area, and etching the nitride layer and the substrate through the exposed isolation trench area to form the isolation trench.
Claim 2
Independent Claim
119 words
A method for forming an alignment mark and an isolation trench on a common wafer, the method comprising the steps of: growing a layer of oxide on a semiconductor substrate; depositing a nitride layer on top of the oxide; masking the wafer with a mask having an exposed alignment mark area; etching the nitride layer, the oxide and the substrate through the exposed alignment mark area to form the alignment mark; and forming an isolation trench in the wafer including the steps of masking the wafer to expose the area of the isolation trench and masking the alignment mark area, and etching the nitride layer and the substrate through the exposed isolation trench area to form the isolation trench.
Claim 3
Dependent Claim
50 words
The method of claim 1, further comprising growing liner oxide in the alignment mark and the isolation trench, the alignment mark having an initial depth prior to the growing of the liner oxide, and a final effective depth greater than the initial depth, after the growth of the liner oxide.
Claim 4
Dependent Claim
62 words
The method of claim 2, wherein the step of forming an isolation trench includes depositing a conformal oxide layer on the nitride layer after the isolation trench has been formed, the oxide layer filling the isolation trench and the alignment mark; masking the isolation trench area; substantially removing the oxide layer except for within the isolation trench; and removing the nitride layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-12 | 2002-10-12 | 2003-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-12 | 2006-10-12 | 2007-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-12 | 2010-10-12 | 2011-04-13 | $7700.00 | Window Closed / Lapsed |