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US5578519A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming align key pattern in semiconductor device

Assignee: Samsung Electronics Co Ltd
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Filing: 1995-11-27
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Granted: 1996-11-26
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Expires: 2015-11-27
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Abstract

Abstract A method for forming an align key pattern in a semiconductor device is provided. The method has the steps of forming a first insulating film pattern for defining field regions in a cell array area and an align key pattern area on a semiconductor substrate, forming trenches in the field regions, using the first insulating film pattern as a mask, forming a second insulating film on the whole surface of the semiconductor substrate, filling the trenches, etching the second insulating film formed on the active regions of the cell array area and on the active and field regions of the align key pattern area, to a predetermined thickness, etching back the whole surface of the semiconductor substrate, forming a conductive layer on the whole surface of the semiconductor substrate, and covering a photoresist on the whole surface of the conductive layer. According to the present invention, an align key pattern needed for a photolithography process is obtainable by forming steps in an align key pattern area in a semiconductor device having an STI structure.

Inventors

  • 👤 Yun-hee Cho

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 21:08
CPC Classifications
H; H10; H10W; H10W10/00; H10W46/00; H10W10/01; H10W46/501

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 140 words
A method for forming an align key pattern in a semiconductor device, the method comprising the steps of: forming a first insulating film pattern for defining field regions in a cell array area and an align key pattern area on a semiconductor substrate; forming trenches in said field regions, using said first insulating film pattern as a mask; forming a second insulating film on the whole surface of said semiconductor substrate, while filling said trenches; etching said second insulating film formed on the active regions of said cell array area and on the active and field regions of said align key pattern area, to a predetermined thickness; etching back the whole surface of said semiconductor substrate; forming a conductive layer on the whole surface of said semiconductor substrate; and covering a photoresist on the whole surface of said conductive layer.
Claim 2
Independent Claim 140 words
A method for forming an align key pattern in a semiconductor device, the method comprising the steps of: forming a first insulating film pattern for defining field regions in a cell array area and an align key pattern area on a semiconductor substrate; forming trenches in said field regions, using said first insulating film pattern as a mask; forming a second insulating film on the whole surface of said semiconductor substrate, while filling said trenches; etching said second insulating film formed on the active regions of said cell array area and on the active and field regions of said align key pattern area, to a predetermined thickness; etching back the whole surface of said semiconductor substrate; forming a conductive layer on the whole surface of said semiconductor substrate; and covering a photoresist on the whole surface of said conductive layer.
Claim 3
Dependent Claim 28 words
A method for forming an align key pattern in a semiconductor device as claimed in claim 1, wherein said second insulating film is formed of an oxide film.
Claim 4
Dependent Claim 33 words
A method for forming an align key pattern in a semiconductor device as claimed in claim 1, wherein said conductive layer is formed of one of a doped polysilicon and a tungsten silicide.
Claim 5
Dependent Claim 53 words
A method for forming an align key pattern in a semiconductor device as claimed in claim 1, wherein said second insulating film is etched to a predetermined thickness by using a photoresist pattern for exposing the active regions of said cell array area and the whole surface of said align key pattern area.

References Cited (Backward Citations)

US5316966A Cited
US5310691A Cited
US5470782A Cited
US5385861A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-11-26 2000-05-27 2000-11-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-11-26 2004-05-27 2004-11-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-11-26 2008-05-27 2008-11-26 $7700.00 Window Closed / Lapsed

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