US5733801A
Expired / Lapsed
US
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Method of making a semiconductor device with alignment marks
Assignee: Toshiba Corp
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Filing: 1996-07-01
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Granted: 1998-03-31
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Expires: 2016-07-01
Abstract
Abstract A first trench is formed in an element-separating region on the surface of a semiconductor substrate, and a second trench is formed in an alignment mark region thereof. When a first insulating substance is deposited on the substrate surface so as to bury the first and second trenches, a first insulating film is formed into a recessed shape in both the first and second trenches. A second insulating substance having an etching rate slower than that of the first insulating substance is formed on the first insulating film, and further etched to leave the second insulating film only over the second trench. The overall thickness of the device is reduced in such a way that the upper surface of the first insulating film in the first trench becomes flush with the semiconductor substrate surface. A part of the surface of the insulating substance on the alignment mark portion projects so as to be usable as an alignment mark. Alternatively, when a first trench is formed extending to both the element-separating and alignment mark regions and further when an insulating film is deposited on the substrate surface so as to bury both the first and second trenches, a first projecting insulating film can be formed between the two trenches. A second insulating film whose etching rate is slower than that of the first insulating film is formed on the projecting insulating film and further etched to leave the second insulating film so as to cover only the first projecting insulating film. The overall thickness is reduced in such a way that the upper surface of the first insulating film becomes flush with the semiconductor substrate surface, and further the remaining second insulating film is removed. The remaining first insulating film is usable as an alignment mark portion.
Inventors
- 👤 Hiroshi Gojohbori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:29
CPC Classifications
H; H10; H10P; H10P95/00; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P52/00; H10P95/70; H10W; H10W46/00; H10W46/301; H10W46/501
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
213 words
A method of manufacturing a semiconductor device, the method comprising: forming a first trench in an element-separating region and a second trench in an alignment mark-forming region, wherein both said element-separating region and said alignment mark-forming region are disposed on a semiconductor substrate; depositing a first insulating substance all over a surface of the device, to form a first film recessed at a central portion of each of the first and second trenches according to shapes of the first and second trenches; depositing a second insulating substance having a first etching rate smaller than a second etching rate of the first insulating substance over the first insulating substance, to form a second film only on the first insulating substance in the second trench; reducing a device thickness over the entire surface of the device so that a portion of an upper surface of the first film in the first trench becomes flush with a portion of an upper surface of the semiconductor substrate; and completely removing the second film on the first insulating substance in the second trench, wherein a portion of an upper surface of the first film in the second trench in said alignment mark-forming region is different in level from said portion of said upper surface of the semiconductor substrate.
Claim 2
Independent Claim
213 words
A method of manufacturing a semiconductor device, the method comprising: forming a first trench in an element-separating region and a second trench in an alignment mark-forming region, wherein both said element-separating region and said alignment mark-forming region are disposed on a semiconductor substrate; depositing a first insulating substance all over a surface of the device, to form a first film recessed at a central portion of each of the first and second trenches according to shapes of the first and second trenches; depositing a second insulating substance having a first etching rate smaller than a second etching rate of the first insulating substance over the first insulating substance, to form a second film only on the first insulating substance in the second trench; reducing a device thickness over the entire surface of the device so that a portion of an upper surface of the first film in the first trench becomes flush with a portion of an upper surface of the semiconductor substrate; and completely removing the second film on the first insulating substance in the second trench, wherein a portion of an upper surface of the first film in the second trench in said alignment mark-forming region is different in level from said portion of said upper surface of the semiconductor substrate.
Claim 3
Dependent Claim
16 words
The method of claim 1, wherein the reducing of the device thickness includes an anisotropic etching.
Claim 4
Dependent Claim
18 words
The method of claim 1, wherein the forming of the second film includes laminating a plurality of films.
Claim 5
Dependent Claim
58 words
The method of claim 1, wherein the second film is selected from the group consisting of a silicon nitride film, a polycrystalline silicon film, a carbon film, a high melting point metal film, a high melting point metal silicide film, a laminated film of the high melting point metal film and the high melting point metal silicide film.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein the reducing of the device thickness includes polishing.
Claim 7
Independent Claim
246 words
A method of manufacturing a semiconductor device, the method comprising: depositing a first film on a semiconductor substrate; forming at least one trench by removing the first film and the semiconductor substrate in both an element-separating region and an alignment mark region, both said element-separating and said alignment mark regions disposed on a surface of the semiconductor substrate, said alignment mark region having an alignment mark portion thereon, wherein said first film is disposed on said alignment mark portion; forming a second film by depositing an insulating substance all over the surface of the semiconductor substrate and the first film in such a way that the at least one trench is filled and a projection portion is formed, said projection portion including the alignment mark portion and the first film disposed on the alignment mark portion; forming a third film only on a side surface and an upper surface of the projection portion; reducing a thickness of the device so that a portion of an upper surface of the second film in said element-separating region becomes flush with a portion of the surface of the semiconductor substrate and said third film remains only on said side surface of said projection portion; and completely removing the third film remaining on the side surface of the projection portion, wherein a portion of an upper surface of the second film in said projection portion is different in level from said portion of the upper surface of the semiconductor substrate.
Claim 8
Independent Claim
246 words
A method of manufacturing a semiconductor device, the method comprising: depositing a first film on a semiconductor substrate; forming at least one trench by removing the first film and the semiconductor substrate in both an element-separating region and an alignment mark region, both said element-separating and said alignment mark regions disposed on a surface of the semiconductor substrate, said alignment mark region having an alignment mark portion thereon, wherein said first film is disposed on said alignment mark portion; forming a second film by depositing an insulating substance all over the surface of the semiconductor substrate and the first film in such a way that the at least one trench is filled and a projection portion is formed, said projection portion including the alignment mark portion and the first film disposed on the alignment mark portion; forming a third film only on a side surface and an upper surface of the projection portion; reducing a thickness of the device so that a portion of an upper surface of the second film in said element-separating region becomes flush with a portion of the surface of the semiconductor substrate and said third film remains only on said side surface of said projection portion; and completely removing the third film remaining on the side surface of the projection portion, wherein a portion of an upper surface of the second film in said projection portion is different in level from said portion of the upper surface of the semiconductor substrate.
Claim 9
Dependent Claim
18 words
The method of claim 6, wherein the forming of the third film includes laminating a plurality of films.
Claim 10
Dependent Claim
60 words
The method of claim 6, wherein the third film is a film selected from the group consisting of a silicon nitride film, a polycrystalline silicon film, a carbon film, a high melting point metal film, a high melting point metal silicide film, a laminated film of the high melting point metal film and the high melting point metal silicide film.
Claim 11
Dependent Claim
16 words
The method of claim 6, wherein the reducing of the device thickness includes an anisotropic etching.
Claim 12
Dependent Claim
14 words
The method of claim 6, wherein the reducing of the device thickness includes polishing.
Claim 13
Dependent Claim
24 words
The method of claim 6, wherein the third film has a first etching rate smaller than a second etching rate of the second film.
Claim 14
Dependent Claim
60 words
The method of claim 11, wherein the third film is a film selected from the group consisting of a silicon nitride film, a polycrystalline silicon film, a carbon film, a high melting point metal film, a high melting point metal silicide film, a laminated film of the high melting point metal film and the high melting point metal silicide film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |