Event phase modulator for integrated circuit tester

Claim 2

A drive circuit for an integrated circuit tester for producing a phase modulated output TEST signal in response to an input sequence of vector data values, wherein each vector data value references a state and a time; the drive circuit comprising: first means for receiving each vector data value and producing an indicating signal (D) of a state referenced by the vector data value and a timing signal (TD) having a pulse occurring at a time referenced by the vector data value; and second means for receiving said indicating signal and said timing signal, for sampling the state of said indicating signal in response to said timing signal pulse and, after a delay following said timing signal pulse, for producing said output TEST signal of a state determined by the sampled state of said indicating signal, wherein said delay varies with time.

Claim 3

The drive circuit in accordance with claim 1 wherein said second means comprises: third means for receiving and delaying said timing signal with said delay that varies with time to produce a delayed timing signal, a first-in, first-out (FIFO) buffer having a data input, a shift-in input, a data output, and a shift-out input, wherein said data input receives said indicating signal, said shift-in input receives said timing signal, and said shift-out input receives said delayed timing signal, wherein said FIFO buffer samples the state of said indicating signal and shifts in a control bit representing the sampled current state in response to each pulse of said timing signal, and wherein said FIFO buffer shifts out its longest stored control bit at said data output in response to each pulse of said delayed timing signal; and fourth means for producing the TEST signal in response to the control bit shifted out of said FIFO buffer.

Claim 4

The drive circuit in accordance with claim 2 wherein said third means comprises: a pattern generator receiving said timing signal for producing output delay data having a value set in response to each pulse of said timing signal, and a programmable delay circuit receiving said delay data and receiving and delaying said timing signal by an amount determined by the value of said delay data thereby to produce said delayed timing data.

Claim 5

The drive circuit in accordance with claim 3 wherein a manner in which the pattern generator, in response to each pulse of said timing signal, sets the delay data to a value determined by programming data provided as input to said pattern generator.

Claim 6

A circuit for producing a phase modulated output signal in response to an input indicating signal (D) having a succession of states and an input timing signal (TD) having a succession of pulses, the circuit comprising: a pattern generator receiving said timing signal for producing output delay data having a value set in response to each pulse of said timing signal; a programmable delay circuit receiving said delay data and receiving and delaying said timing signal by an amount determined by the value of said delay data thereby to produce said delayed timing data; a first-in, first-out (FIFO) buffer having a data input, a shift-in input, a data output, and a shift-out input, wherein said data input receives said indicating signal, said shift-in input receives said timing signal, and said shift-out input receives said delayed timing signal, wherein said FIFO buffer samples the state of said indicating signal and stores a control bit representing the sampled current state in response to each pulse of said timing signal, and wherein said FIFO buffer shifts out its longest stored control bit at said data output in response to each pulse of said delayed timing signal; and fourth means for producing the TEST signal in response to the control bit shifted out of said FIFO buffer.

Claim 7

A circuit for producing a phase modulated output signal in response to an input indicating signal (D) having a succession of states and an input timing signal (TD) having a succession of pulses, the circuit comprising: a pattern generator receiving said timing signal for producing output delay data having a value set in response to each pulse of said timing signal; a programmable delay circuit receiving said delay data and receiving and delaying said timing signal by an amount determined by the value of said delay data thereby to produce said delayed timing data; a first-in, first-out (FIFO) buffer having a data input, a shift-in input, a data output, and a shift-out input, wherein said data input receives said indicating signal, said shift-in input receives said timing signal, and said shift-out input receives said delayed timing signal, wherein said FIFO buffer samples the state of said indicating signal and stores a control bit representing the sampled current state in response to each pulse of said timing signal, and wherein said FIFO buffer shifts out its longest stored control bit at said data output in response to each pulse of said delayed timing signal; and fourth means for producing the TEST signal in response to the control bit shifted out of said FIFO buffer.

Claim 8

The circuit in accordance with claim 5 wherein a manner in which the pattern generator responds to each pulse of said timing signal by setting the delay data to a value determined by programming data provided as input to said pattern generator.

Claim 9

A drive circuit for an integrated circuit tester for producing an output TEST signal in response to an input sequence of vector data values, wherein each vector data value references a state and a time, the drive circuit comprising: first means for receiving each vector data value and producing a first indicating signal (D) and a second indicating signal (I) each of a state referenced by the vector data value and a first timing signal TD) and a second timing signal (TI) each having a pulse occurring at a time referenced by the vector data value; second means for receiving said first indicating signal and said first timing signal, for sampling the state of said first indicating signal in response to said first timing signal pulse and, after a first delay following said first timing signal pulse, for producing an output DRIVE signal of a state determined by the sampled state of said first indicating signal, wherein said first delay varies with time; third means for receiving said second indicating signal and said second timing signal, for sampling the state of said second indicating signal in response to said second timing signal pulse and, after a second delay following said second timing signal pulse, for producing an output INHIBIT signal of a state determined by the sampled state of said second indicating signal, wherein said second delay varies with time; and an inhibitable driver receiving said DRIVE and INHIBIT signals and producing said TEST signal in response thereto, wherein the state of said INHIBIT signal determines whether said TEST signal is inhibited or is controlled by the state of said DRIVE signal.

Claim 10

A drive circuit for an integrated circuit tester for producing an output TEST signal in response to an input sequence of vector data values, wherein each vector data value references a state and a time, the drive circuit comprising: first means for receiving each vector data value and producing a first indicating signal (D) and a second indicating signal (I) each of a state referenced by the vector data value and a first timing signal TD) and a second timing signal (TI) each having a pulse occurring at a time referenced by the vector data value; second means for receiving said first indicating signal and said first timing signal, for sampling the state of said first indicating signal in response to said first timing signal pulse and, after a first delay following said first timing signal pulse, for producing an output DRIVE signal of a state determined by the sampled state of said first indicating signal, wherein said first delay varies with time; third means for receiving said second indicating signal and said second timing signal, for sampling the state of said second indicating signal in response to said second timing signal pulse and, after a second delay following said second timing signal pulse, for producing an output INHIBIT signal of a state determined by the sampled state of said second indicating signal, wherein said second delay varies with time; and an inhibitable driver receiving said DRIVE and INHIBIT signals and producing said TEST signal in response thereto, wherein the state of said INHIBIT signal determines whether said TEST signal is inhibited or is controlled by the state of said DRIVE signal.

Claim 11

The drive circuit in accordance with claim 7 wherein said second means comprises: fourth means for receiving and delaying said first timing signal with said first delay that varies with time to produce a delayed first timing signal; and a first-in, first-out (FIFO) buffer having a data input, a shift-in input, a data output, and a shift-out input, wherein said data input receives said first indicating signal, said shift-in input receives said first timing signal, and said shift-out input receives said delayed first timing signal, wherein said FIFO buffer samples the state of said first indicating signal and shifts in a control bit representing the sampled current state in response to each pulse of said timing signal, and wherein said FIFO buffer shifts out its longest stored control bit at said data output in response to each pulse of said delayed first timing signal thereby to produce said DRIVE signal.

Claim 12

A drive circuit for an integrated circuit tester for producing an output TEST signal in response to an input sequence of vector data values, wherein each vector data value references a state and a time, the drive circuit comprising: means for receiving each vector data value and producing four indicating signals (DH,DL,IH, and IL), each of a state referenced by the vector data value and for producing four timing signals (TDH, TDL, TIH, and TIL) each conveying a pulse at a time referenced by the vector data value; first, second, third and fourth event phase modulators, each receiving a separate one of said four indicating signals and a separate one of said four timing signals, each sampling the state of its received indicating signal in response to a pulse of its received timing signal and, after a delay following the timing signal pulse, for producing an output control pulse of a state determined by the sampled state of its received indicating signal, wherein said delay varies with time; a first type SR flip-flop having a set input receiving the output control pulse of said first event phase modulator, having a reset input receiving the output control pulse of said second event phase modulator, and producing an output DRIVE signal; a second type SR flip-flop having a set input receiving the output control pulse of said third event phase modulator, having a reset input receiving the output control pulse of said fourth event phase modulator, and producing an output INHIBIT signal; and an inhibitable driver receiving said DRIVE and INHIBIT signals and producing said TEST signal in response thereto, wherein the state of said INHIBIT signal determines whether said TEST signal is inhibited or is controlled by the state of said DRIVE signal.

Claim 13

A drive circuit for an integrated circuit tester for producing an output TEST signal in response to an input sequence of vector data values, wherein each vector data value references a state and a time, the drive circuit comprising: means for receiving each vector data value and producing four indicating signals (DH,DL,IH, and IL), each of a state referenced by the vector data value and for producing four timing signals (TDH, TDL, TIH, and TIL) each conveying a pulse at a time referenced by the vector data value; first, second, third and fourth event phase modulators, each receiving a separate one of said four indicating signals and a separate one of said four timing signals, each sampling the state of its received indicating signal in response to a pulse of its received timing signal and, after a delay following the timing signal pulse, for producing an output control pulse of a state determined by the sampled state of its received indicating signal, wherein said delay varies with time; a first type SR flip-flop having a set input receiving the output control pulse of said first event phase modulator, having a reset input receiving the output control pulse of said second event phase modulator, and producing an output DRIVE signal; a second type SR flip-flop having a set input receiving the output control pulse of said third event phase modulator, having a reset input receiving the output control pulse of said fourth event phase modulator, and producing an output INHIBIT signal; and an inhibitable driver receiving said DRIVE and INHIBIT signals and producing said TEST signal in response thereto, wherein the state of said INHIBIT signal determines whether said TEST signal is inhibited or is controlled by the state of said DRIVE signal.

Claim 14

The drive circuit in accordance with claim 9 wherein each said second means comprises: means for receiving and delaying said one of said timing signals with said delay that varies with time to produce a delayed timing signal; and a first-in, first-out (FIFO) buffer having a data input, a shift-in input, a data output, and a shift-out input, wherein said data input receives one of said indicating signals, said shift-in input receives said one of said timing signals, and said shift-out input receives said delayed timing signal, wherein said FIFO buffer samples the state of said one of said indicating signals and shifts in a control bit representing the sampled current state in response to each pulse of said one of said timing signals, and wherein said FIFO buffer shifts out its longest stored control bit at said data output in response to each pulse of said delayed first timing signal thereby to produce an output control pulse.

Claim 17

The method in accordance with claim 11 wherein the step of generating said indicating signal and said timing signal comprises the substep of decoding an input sequence of vector data values, wherein each successive vector data value indicates a successive state of said indicating signal and a time of a successive pulse of said timing signal.