Method for performing transistor-level static timing analysis of a logic circuit

Claim 3

The method of claim 1, further comprising the step of: simulating a function of the logic circuit by providing the simulation pattern to an input of the logic circuit.

Claim 4

The method of claim 2, further comprising the step of: measuring a result of the simulation pattern on the input of the logic circuit.

Claim 5

The method of claim 3 wherein the result indicates a delay associated with the provision of the input signal and the output of the logic circuit.

Claim 6

The method of claim 3, further comprising the steps of: determining whether the result is less than a previous result of a previous simulation pattern on the logic circuit; storing the previous result of the previous simulation pattern in a memory when the previous result is greater than the result; and storing the result of the simulation pattern in the memory when the previous result is less than the result.

Claim 7

The method of claim 3, further comprising the steps of: determining whether the result is less than a previous result of a previous simulation pattern on the node of the clock circuit; storing the previous result of the previous simulation pattern in a memory when the previous result is less than the result; and storing the result of the simulation pattern in the memory when the previous result is greater than the result.

Claim 8

The method of claim 1 wherein the step of computing the sensitization condition, further comprises the step of: determining when the output of the logic circuit will not be in an undesired logic state after the input signal has transitioned from the first logic state to the second logic state.

Claim 9

The method of claim 1 wherein the step of computing the sensitization condition, further comprises the step of: determining when the output of the logic circuit will be in a desired logic state before the input signal has transitioned from the first logic state to the second logic state.

Claim 10

The method of claim 1 wherein a step of computing the sensitization condition, further comprises the step of: determining when the output of the logic circuit will be in a desired logic state after an input signal has transitioned from a first logic state to a second logic state.

Claim 11

The method of claim 9 wherein the step of computing the sensitization condition, further comprises the step of: determining when output of the logic circuit will not be in an undesired logic state after the input signal has transitioned from the first logic state to the second logic state.

Claim 12

A data processing system, comprising: a memory for storing a model of a logic circuit; and a data processor for computing a first signal being provided to the logic circuit and a second signal being output by the logic circuit in response to the first signal, the data processor computing the delay by determining a sensitization condition corresponding to the first signal and applying a generated signal which has the sensitization condition corresponding to the first signal provided to the logic circuit.

Claim 13

A data processing system, comprising: a memory for storing a model of a logic circuit; and a data processor for computing a first signal being provided to the logic circuit and a second signal being output by the logic circuit in response to the first signal, the data processor computing the delay by determining a sensitization condition corresponding to the first signal and applying a generated signal which has the sensitization condition corresponding to the first signal provided to the logic circuit.

Claim 14

The data processing system of claim 11 wherein the sensitization condition determines when the output of the logic circuit will be in a desired logic state after an input signal has transitioned from a first logic level to a second logic level.

Claim 15

The data processing system of claim 11 wherein the sensitization condition determines when output of the logic circuit will be in a desired logic state before the input signal has transitioned from the first logic level to the second logic level.

Claim 16

The data processing system of claim 11 wherein the sensitization condition determines when output of the logic circuit will not be in an undesired logic state after the input signal has transitioned from the first logic level to the second logic level.

Claim 17

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for performing a timing analysis of a logic circuit, said method steps comprising: identifying an input signal transition and an output signal transition of the logic circuit; computing a sensitization condition corresponding to the input signal transition and the output signal transition; using the sensitization condition to identify a worst case condition; and generating a simulation pattern which enables an output of the logic circuit to transition from a first logic state to a second logic state by applying a generated signal which corresponds to the sensitization condition.

Claim 18

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for performing a timing analysis of a logic circuit, said method steps comprising: identifying an input signal transition and an output signal transition of the logic circuit; computing a sensitization condition corresponding to the input signal transition and the output signal transition; using the sensitization condition to identify a worst case condition; and generating a simulation pattern which enables an output of the logic circuit to transition from a first logic state to a second logic state by applying a generated signal which corresponds to the sensitization condition.

Claim 19

The program storage device of claim 15 embodying the program of instructions executable by the machine to perform method steps, said method steps further comprising a step of: simulating a function of the logic circuit by providing the simulation pattern to an input of the logic circuit, wherein a result indicates a delay associated with the provision of a first one of a plurality of input signals and the output generated by the logic circuit.

Claim 20

The program storage device of claim 15 embodying the program of instructions executable by the machine to perform method steps, said method steps further comprising a step of: determining when the output of the logic circuit will be in a desired logic state after an input signal has transitioned from a first logic state to a second logic state.

Claim 21

The program storage device of claim 15 embodying the program of instructions executable by the machine to perform method steps, said method steps further comprising a step of: determining when the output of the logic circuit will not be in an undesired logic state after the input signal has transitioned from the first logic state to the second logic state.

Claim 22

The program storage device of claim 18 embodying the program of instructions executable by the machine to perform method steps, said method steps further comprising a step of: determining when the output of the logic circuit will be in a desired logic state before the input signal has transitioned from the first logic state to the second logic state.