Semiconductor memory device with peripheral dummy cell array

Claim 2

A semiconductor memory cell device comprising a cell array including a memory cell array section having a plurality of memory cells arranged in a matrix for storing information, said memory cell array section having an outer peripheral perimeter, and a dummy cell array section having a plurality of dummy cells arranged in areas adjacent all sides of said outer peripheral perimeter of said memory cell array section, each of said memory cells including a memory cell transistor and a storage capacitor having a bottom electrode and a top electrode both overlying said memory cell transistor for storing electric charge supplied from said memory cell transistor, each of said dummy cells including a dummy cell transistor having a configuration substantially the same as a configuration of said memory cell transistors, and a driving circuit comprising dummy cells, for driving said memory cell section.

Claim 3

A semiconductor memory device as defined in claim 1, wherein said top electrodes of said storage capacitors have a substantially uniform surface extending between said memory cell section and said dummy cell section.

Claim 4

A semiconductor memory device as defined in claim 1, wherein each of said dummy cells further includes a dummy storage capacitor overlying said dummy cell transistor for storing electric charge supplied from said dummy cell transistor, said dummy cell constituting redundant memory cells for said memory cells.

Claim 5

A semiconductor memory device as defined in claim 1, wherein said storage capacitor is of a stacked type.

Claim 6

A semiconductor memory device as defined in claim 1, wherein each said dummy cells further includes a storage capacitor, and is arranged as a part of the matrix of said memory cells at a constant pitch.

Claim 7

A semiconductor memory device as defined in claim 5, wherein each said dummy transistor comprising said driving circuit has a first diffused region connected to a digit line of said memory cell array and a gate connected to a word line of said memory cell array.

Claim 8

A semiconductor memory device as defined in claim 6, wherein each said dummy cell comprising said driving circuit transistor has a second diffused region connected through a first interconnect layer to a second interconnect layer disposed as overlying said storage capacitor, said first interconnect layer underlying said storage capacitor.

Claim 9

The semiconductor memory device of claim 3, wherein each of said dummy cell transistors comprise two diffusion regions free of contact with a bottom electrode of the corresponding overlying dummy storage capacitor.

Claim 10

The semiconductor memory device of claim 6, wherein each said dummy cell transistor comprising said driving circuit further comprises a second diffusion region connected to a digit line of a sense amplifier.

Claim 11

A semiconductor memory cell device comprising a cell array including a memory cell array section having a plurality of memory cells arranged in a matrix for storing information and a dummy cell array section having a plurality of dummy cells arranged in an outer peripheral area of said memory cell array section, each of said memory cells including a memory cell transistor and a storage capacitor having a bottom electrode and a top electrode both overlying said memory cell transistor for storing electric charge supplied from said memory cell transistor, each of said dummy cells including a dummy cell transistor having a configuration substantially the same as a configuration of said memory cell transistors, at least a part of said dummy cell transistors constituting a driver circuit, for driving said memory cell section; wherein each said dummy transistor has a first diffused region connected to a digit line of said memory cell array and a gate connected to a word line of said memory cell array; and wherein each said dummy cell transistor has a second diffused region connected through a first interconnect layer to a second interconnect layer disposed as overlying said storage capacitor, said first interconnect layer underlying said storage capacitor.

Claim 12

A semiconductor memory cell device comprising a cell array including a memory cell array section having a plurality of memory cells arranged in a matrix for storing information and a dummy cell array section having a plurality of dummy cells arranged in an outer peripheral area of said memory cell array section, each of said memory cells including a memory cell transistor and a storage capacitor having a bottom electrode and a top electrode both overlying said memory cell transistor for storing electric charge supplied from said memory cell transistor, each of said dummy cells including a dummy cell transistor having a configuration substantially the same as a configuration of said memory cell transistors, at least a part of said dummy cell transistors constituting a driver circuit, for driving said memory cell section; wherein each said dummy transistor has a first diffused region connected to a digit line of said memory cell array and a gate connected to a word line of said memory cell array; and wherein each said dummy cell transistor has a second diffused region connected through a first interconnect layer to a second interconnect layer disposed as overlying said storage capacitor, said first interconnect layer underlying said storage capacitor.