US5943684A
Expired / Lapsed
US
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Method and system of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system
Assignee: International Business Machines Corp
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Filing: 1997-04-14
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Granted: 1999-08-24
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Expires: 2017-04-14
Abstract
Abstract A method and system of providing a cache-coherency protocol for maintaining cache coherency within a multi-processor data-processing system is disclosed. In accordance with the method and system of the present invention, each processor has a cache hierarchy of at least a first-level cache and a second-level cache, and the first-level cache is upstream of the second-level cache. Each of the caches includes multiple cache lines, each associated to a state-bit field utilized for identifying at least six different states of the cache lines, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state. In response to an indication of a cache line containing a copy of information that was most recently accessed, the state of the cache line is transitioned from the Invalid state to the Recently-Read state. In response to an information modification of a cache line in the first-level cache without performing a linefill operation, the state of the cache line is transitioned from the Invalid state to the Upstream-Undefined state.
Inventors
- 👤 Ravi Kumar Arimilli
- 👤 John Steven Dodson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0811
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
174 words
A method of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system, each processor within said multiprocessor data-processing system having a cache hierarchy of at least a first-level cache and a second-level cache, wherein said first-level cache is upstream of said second-level cache and each of said caches includes a plurality of cache lines, said method comprising the steps of: associating a state-bit field with each of said plurality of cache lines, wherein said state bit field is utilized to identify a plurality of states, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state; in response to an indication that a cache line contains a copy of information that was most recently read, transitioning an associated state-bit field from said Invalid state to said Recently-Read state; and in response to an information modification in a cache line in said first-level cache without performing a linefill operation, transitioning an associated state-bit field from said Invalid state to said Upstream-Undefined state.
Claim 2
Independent Claim
174 words
A method of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system, each processor within said multiprocessor data-processing system having a cache hierarchy of at least a first-level cache and a second-level cache, wherein said first-level cache is upstream of said second-level cache and each of said caches includes a plurality of cache lines, said method comprising the steps of: associating a state-bit field with each of said plurality of cache lines, wherein said state bit field is utilized to identify a plurality of states, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state; in response to an indication that a cache line contains a copy of information that was most recently read, transitioning an associated state-bit field from said Invalid state to said Recently-Read state; and in response to an information modification in a cache line in said first-level cache without performing a linefill operation, transitioning an associated state-bit field from said Invalid state to said Upstream-Undefined state.
Claim 3
Dependent Claim
27 words
The method according to claim 1, wherein said method further includes a step of transitioning an associated state-bit field from said Recently-Read state to said Invalid state.
Claim 4
Dependent Claim
27 words
The method according to claim 1, wherein said method further includes a step of transitioning an associated state-bit field from said Recently-Read state to said Modified state.
Claim 5
Dependent Claim
27 words
The method according to claim 1, wherein said method further includes a step of transitioning an associated state-bit field from said Recently-Read state to said Shared state.
Claim 6
Dependent Claim
27 words
The method according to claim 1, wherein said method further includes a step of transitioning an associated state-bit field from said Modified state to said Shared state.
Claim 7
Dependent Claim
169 words
A cache memory having a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system, each processor within said multiprocessor data-processing system having a cache hierarchy of at least a first-level cache and a second-level cache, wherein said first-level cache is upstream of said second-level cache, said cache memory comprising: a plurality of cache lines; a state-bit field associated with each of said plurality of cache lines, said state bit field is utilized to identify a plurality of states, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state; means for transitioning an associated state-bit field from said Invalid state to said Recently-Read state, in response to an indication that a cache line contains a copy of information that was most recently read; and means for transitioning an associated state-bit field from said Invalid state to said Upstream-Undefined state, in response to an information modification in a cache line in said first-level cache without performing a linefill operation.
Claim 8
Dependent Claim
169 words
A cache memory having a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system, each processor within said multiprocessor data-processing system having a cache hierarchy of at least a first-level cache and a second-level cache, wherein said first-level cache is upstream of said second-level cache, said cache memory comprising: a plurality of cache lines; a state-bit field associated with each of said plurality of cache lines, said state bit field is utilized to identify a plurality of states, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state; means for transitioning an associated state-bit field from said Invalid state to said Recently-Read state, in response to an indication that a cache line contains a copy of information that was most recently read; and means for transitioning an associated state-bit field from said Invalid state to said Upstream-Undefined state, in response to an information modification in a cache line in said first-level cache without performing a linefill operation.
Claim 9
Dependent Claim
29 words
The cache memory according to claim 6, wherein said cache memory further includes a mean for transitioning an associated state-bit field from said Recently-Read state to said Invalid state.
Claim 10
Dependent Claim
29 words
The cache memory according to claim 6, wherein said cache memory further includes a means for transitioning an associated state-bit field from said Recently-Read state to said Modified state.
Claim 11
Dependent Claim
29 words
The cache memory according to claim 6, wherein said cache memory further includes a means for transitioning an associated state-bit field from said Recently-Read state to said Shared state.
Claim 12
Dependent Claim
29 words
The cache memory according to claim 6, wherein said cache memory further includes a means for transitioning an associated state-bit field from said Modified state to said Shared state.
Claim 13
Dependent Claim
200 words
A multiprocessor data-processing system comprising: a plurality of processing units; a system memory coupled to said plurality of processing units; a first-level cache memory included within each of said plurality of processing units; a plurality of second-level cache memories, wherein each of said plurality of second-level cache memories is associated one of said first-level cache memory, wherein said first-level cache is upstream of said second-level cache; wherein each of said cache memories having a cache-coherency protocol for maintaining cache coherency, further includes: a plurality of cache lines; a state-bit field associated with each of said plurality of cache lines, said state bit field is utilized to identify a plurality of states, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state; means for transitioning an associated state-bit field from said Invalid state to said Recently-Read state, in response to an indication that a cache line containing a copy of information that was most recently read; and means for transitioning an associated state-bit field from said Invalid state to said Upstream-Undefined state, in response to an information modification in a cache line in said first-level cache without performing a linefill operation.
Claim 14
Dependent Claim
200 words
A multiprocessor data-processing system comprising: a plurality of processing units; a system memory coupled to said plurality of processing units; a first-level cache memory included within each of said plurality of processing units; a plurality of second-level cache memories, wherein each of said plurality of second-level cache memories is associated one of said first-level cache memory, wherein said first-level cache is upstream of said second-level cache; wherein each of said cache memories having a cache-coherency protocol for maintaining cache coherency, further includes: a plurality of cache lines; a state-bit field associated with each of said plurality of cache lines, said state bit field is utilized to identify a plurality of states, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state; means for transitioning an associated state-bit field from said Invalid state to said Recently-Read state, in response to an indication that a cache line containing a copy of information that was most recently read; and means for transitioning an associated state-bit field from said Invalid state to said Upstream-Undefined state, in response to an information modification in a cache line in said first-level cache without performing a linefill operation.
Claim 15
Dependent Claim
32 words
The multiprocessor data-processing system according to claim 11, wherein each of said cache memories further includes a means for transitioning an associated state-bit field from said Recently-Read state to said Invalid state.
Claim 16
Dependent Claim
32 words
The multiprocessor data-processing system according to claim 11, wherein each of said cache memories further includes a means for transitioning an associated state-bit field from said Recently-Read state to said Modified state.
Claim 17
Dependent Claim
32 words
The multiprocessor data-processing system according to claim 11, wherein each of said cache memories further includes a means for transitioning an associated state-bit field from said Recently-Read state to said Shared state.
Claim 18
Dependent Claim
32 words
The multiprocessor data-processing system according to claim 11, wherein each of said cache memories further includes a means for transitioning an associated state-bit field from said Modified state to said Shared state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |