US5375216A
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US
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Apparatus and method for optimizing performance of a cache memory in a data processing system
Assignee: NXP USA Inc
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Filing: 1992-02-28
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Granted: 1994-12-20
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Expires: 2012-02-28
Abstract
Abstract A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.
Inventors
- 👤 William C. Moyer
- 👤 John H. Arends
- 👤 Christopher E. White
- 👤 Keith E. Diefendorff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30047; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0862; G06F9/30043; G06F9/30181; G06F9/38; G06F9/3824; G06F9/383; G06F9/3836; G06F9/3842; G06F9/3861; G06F9/3863; G06F2212/00; G06F2212/60; G06F2212/6028
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
234 words
A data processor having a cache memory, comprising: an interface circuit for receiving a data processing instruction; a decoder coupled to the interface circuit for receiving and decoding the data processing instruction, the decoder decoding a first portion of the data processing instruction to provide a first control signal, the decoder decoding a second portion of the data processing instruction to provide a second control signal, the decoder decoding a third portion of the data processing instruction to provide a register, the decoder decoding a fourth portion of the data processing instruction to provide an address value; a cache memory access circuit coupled to the decoder for receiving the address value, the cache memory access circuit selectively accessing the cache memory in response to the address value, the cache memory access means providing a third control signal indicating when the address value corresponds to a memory location in the cache memory; and cache control means for selectively performing a first cache memory access in response to the first control signal, the second control signal, the third control signal, and the address value when the register is one of a first plurality of registers and the cache control means performing a second cache memory access in response to the first control signal, the second control signal, the third control signal, and the address value when the register is one of a second plurality of registers.
Claim 2
Dependent Claim
234 words
A data processor having a cache memory, comprising: an interface circuit for receiving a data processing instruction; a decoder coupled to the interface circuit for receiving and decoding the data processing instruction, the decoder decoding a first portion of the data processing instruction to provide a first control signal, the decoder decoding a second portion of the data processing instruction to provide a second control signal, the decoder decoding a third portion of the data processing instruction to provide a register, the decoder decoding a fourth portion of the data processing instruction to provide an address value; a cache memory access circuit coupled to the decoder for receiving the address value, the cache memory access circuit selectively accessing the cache memory in response to the address value, the cache memory access means providing a third control signal indicating when the address value corresponds to a memory location in the cache memory; and cache control means for selectively performing a first cache memory access in response to the first control signal, the second control signal, the third control signal, and the address value when the register is one of a first plurality of registers and the cache control means performing a second cache memory access in response to the first control signal, the second control signal, the third control signal, and the address value when the register is one of a second plurality of registers.
Claim 3
Dependent Claim
26 words
The data processor having the cache memory of claim 1 wherein the second plurality of registers each store a constant value which may not be modified.
Claim 4
Dependent Claim
34 words
The data processor having the cache memory of claim 1 wherein the first cache memory access is a load operation which accesses a data value stored in a memory location in the cache memory.
Claim 5
Dependent Claim
61 words
The data processor having the cache memory of claim 1 wherein the second cache memory access operation is a cache touch load operation when the second control signal is a first value, a cache flush load operation when the second control signal is a second value, and a cache allocate load operation when the second control signal is a third value.
Claim 6
Dependent Claim
61 words
The data processor having the cache memory of claim 4 wherein a data value is stored in a cache memory location indicated by the address value provided by the fourth portion of the data processing instruction during execution of the cache touch load operation, the cache touch load operation being executed before a cache load operation accesses the cache memory location.
Claim 7
Dependent Claim
55 words
The data processor having the cache memory of claim 4 wherein a data value stored in a cache memory location indicated by the address value provided by the fourth portion of the data processing instruction is cleared in the cache memory and stored in an external memory during execution of the cache flush load operation.
Claim 8
Dependent Claim
45 words
The data processor having the cache memory of claim 4 wherein a cache memory location indicated by the address value provided by the fourth portion of the data processing instruction is allocated for a subsequent cache store operation during execution of the cache allocate operation.
Claim 9
Dependent Claim
31 words
The data processor having the cache memory of claim 1 wherein the second portion of the data processing instruction is an instruction suffix indicating a bit width of a data value.
Claim 10
Dependent Claim
36 words
The data processor having the cache memory of claim 8 wherein the second cache memory access operation is a cache touch load operation when the instruction suffix indicates the bit width is equal to a byte.
Claim 11
Dependent Claim
36 words
The data processor having the cache memory of claim 8 wherein the second cache memory access operation is a cache flush load operation when the instruction suffix indicates the bit width is equal to a word.
Claim 12
Dependent Claim
36 words
The data processor having the cache memory of claim 8 wherein the second cache memory access operation is a cache allocate load operation when the instruction suffix indicates the bit width is equal to a half-word.
Claim 13
Dependent Claim
33 words
The data processor having the cache memory of claim 1 wherein both the first cache memory access operation and the second cache memory access operation are executed in a user mode of operation.
Claim 14
Dependent Claim
34 words
The data processor having the cache memory of claim 1 wherein the first portion of the data processing instruction is an opcode which is identical for the first and second cache memory access operations.
Claim 15
Dependent Claim
51 words
The data processor having the cache memory of claim 1 wherein the cache control means provides a transfer code signal to an external user which indicates when the second cache access operation will be executed, the cache control means being coupled to the interface circuit for providing the transfer code signal.
Claim 16
Independent Claim
145 words
A method for executing a cache memory access operation, comprising the steps of: receiving a data processing instruction; decoding a first portion of the data processing instruction to provide an opcode; decoding a second portion of the data processing instruction to provide a first control signal; decoding a third portion of the data processing instruction to provide a register; decoding a fourth portion of the data processing instruction to provide an address value; providing a second control signal to indicate when the address value corresponds to a memory location in a cache memory; selectively accessing the memory location in the cache memory when the address value corresponds thereto; performing a first cache memory access operation when the register is one of a first plurality of registers; and performing a second cache memory access operation when the register is one of a second plurality of registers.
Claim 17
Independent Claim
145 words
A method for executing a cache memory access operation, comprising the steps of: receiving a data processing instruction; decoding a first portion of the data processing instruction to provide an opcode; decoding a second portion of the data processing instruction to provide a first control signal; decoding a third portion of the data processing instruction to provide a register; decoding a fourth portion of the data processing instruction to provide an address value; providing a second control signal to indicate when the address value corresponds to a memory location in a cache memory; selectively accessing the memory location in the cache memory when the address value corresponds thereto; performing a first cache memory access operation when the register is one of a first plurality of registers; and performing a second cache memory access operation when the register is one of a second plurality of registers.
Claim 18
Dependent Claim
40 words
The method of claim 15 wherein the second cache memory access operation is a cache touch load operation when the first opcode is a load opcode and the first control signal indicates a byte size data access should be executed.
Claim 19
Dependent Claim
40 words
The method of claim 15 wherein the second cache memory access operation is a cache flush load operation when the first opcode is a load opcode and the first control signal indicates a word size data access should be executed.
Claim 20
Dependent Claim
40 words
The method of claim 15 wherein the second cache memory access operation is a cache allocate load operation when the first opcode is a load opcode and the first control signal indicates a half-word size data access should be executed.
Claim 21
Dependent Claim
31 words
The method of claim 15 wherein: the first plurality of registers may be written and read; and the second plurality of registers store a constant value which may be read only.
Claim 22
Dependent Claim
81 words
The method of claim 15 wherein the second data processing function further comprises the steps of: storing a first data value in the memory location in the cache memory when the first control signal is a first value; clearing a second data value in the memory location in the cache memory when the first control signal is a second value; and allocating the memory location for a subsequent cache memory store operation when the first control signal is a third value.
Claim 23
Dependent Claim
49 words
The method of claim 20 wherein the first value indicates a bit width of a data access is a byte, the second value indicates the bit width of the data access is a word, and the third value indicates the bit width of the data access is a half-word.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |