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US5943479A
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Method for reducing the rate of interrupts in a high speed I/O controller
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-01-02
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Granted: 1999-08-24
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Expires: 2017-01-02
Abstract
Abstract A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU. The second parameter sets the event time-out, which is the maximum time an event can be pending before posting an interrupt to the CPU. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit handling of the event can be delayed indefinitely.
Inventors
- 👤 Philippe Klein
- 👤 Aviad Wertheimer
- 👤 Gideon Paul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:17
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
187 words
A method to reduce transmit interrupts comprising the steps of: providing a central processing unit (CPU); providing an input/output (I/O) device connected to the CPU, the I/O device having a system bus interface circuit to provide connection to a system bus, a network interface circuit to provide connection to a network system, a buffer memory to handle a plurality of input and output data streams, and a direct memory access (DMA) function device; in the DMA function device, setting a transmit count limit variable to a threshold of consecutive transmit packets transmitted before posting a transmit interrupt to the CPU; setting a transmit time limit variable to a time-out time before posting the transmit interrupt to the CPU; initializing a transmit count counter and a transmit time counter to zero; waiting for a transmission of a packet of data; upon a transmission of a packet of data, waiting for a predetermined event to occur; determining whether the transmit interrupt should be posted to the CPU IN response to a predetermined event; and returning to the step of initializing after posting of the transmit interrupt to the CPU.
Claim 2
Independent Claim
187 words
A method to reduce transmit interrupts comprising the steps of: providing a central processing unit (CPU); providing an input/output (I/O) device connected to the CPU, the I/O device having a system bus interface circuit to provide connection to a system bus, a network interface circuit to provide connection to a network system, a buffer memory to handle a plurality of input and output data streams, and a direct memory access (DMA) function device; in the DMA function device, setting a transmit count limit variable to a threshold of consecutive transmit packets transmitted before posting a transmit interrupt to the CPU; setting a transmit time limit variable to a time-out time before posting the transmit interrupt to the CPU; initializing a transmit count counter and a transmit time counter to zero; waiting for a transmission of a packet of data; upon a transmission of a packet of data, waiting for a predetermined event to occur; determining whether the transmit interrupt should be posted to the CPU IN response to a predetermined event; and returning to the step of initializing after posting of the transmit interrupt to the CPU.
Claim 3
Dependent Claim
19 words
The method to reduce transmit interrupts according to claim 1 wherein the controller device is an input/output (I/O) controller.
Claim 4
Dependent Claim
19 words
The method to reduce transmit interrupts according to claim 1 wherein the controller device is a system bus adapter.
Claim 5
Dependent Claim
86 words
The method to reduce transmit interrupts according to claim 1 wherein the step of determining whether the transmit interrupt should be posted to the CPU in response to the predetermined event comprises the steps of: transmitting the data packet; incrementing the transmit count counter by one; returning to the step of determining if the transmit count counter does not equal the transmit count limit variable; and posting the transmit interrupt to the CPU if the transmit count counter does not equal the transmit count limit variable.
Claim 6
Dependent Claim
87 words
The method to reduce transmit interrupts according to claim 4 wherein the step of determining whether the transmit interrupt should be posted to the CPU in response to the predetermined event comprises the steps of: waiting a specified time unit; incrementing the transmit count counter by one; returning to the step of determining if the transmit time counter does not equal the transmit time limit variable; and posting the transmit interrupt to the CPU if the transmit time counter does not equal the transmit time limit variable.
Claim 7
Independent Claim
185 words
A method to reduce receive interrupts comprising the steps of: providing a central processing unit (CPU); providing an input/output (I/O) device connected to the CPU, the I/O device having a system bus interface circuit to provide connection to a system bus, a network interface circuit to provide connection to a network system, a buffer memory to handle a plurality of input and output data streams, and a direct memory access (DMA) function device; in the DMA function device, setting a receive count limit variable to a threshold of packets received before posting a receive interrupt to the CPU; setting a receive time limit variable to a time-out time before posting the receive interrupt to the CPU; initializing a receive count counter and a receive time counter to zero; waiting for a reception of a packet of data; upon the reception of a packet of data, waiting for a predetermined event to occur; determining whether the receive interrupt should be posted to the CPU IN response to a predetermined event; and returning to the step of initializing after posting of the receive interrupt to the CPU.
Claim 8
Independent Claim
185 words
A method to reduce receive interrupts comprising the steps of: providing a central processing unit (CPU); providing an input/output (I/O) device connected to the CPU, the I/O device having a system bus interface circuit to provide connection to a system bus, a network interface circuit to provide connection to a network system, a buffer memory to handle a plurality of input and output data streams, and a direct memory access (DMA) function device; in the DMA function device, setting a receive count limit variable to a threshold of packets received before posting a receive interrupt to the CPU; setting a receive time limit variable to a time-out time before posting the receive interrupt to the CPU; initializing a receive count counter and a receive time counter to zero; waiting for a reception of a packet of data; upon the reception of a packet of data, waiting for a predetermined event to occur; determining whether the receive interrupt should be posted to the CPU IN response to a predetermined event; and returning to the step of initializing after posting of the receive interrupt to the CPU.
Claim 9
Dependent Claim
19 words
The method to reduce receive interrupts according to claim 6 wherein the controller device is an input/output (I/O) controller.
Claim 10
Dependent Claim
19 words
The method to reduce receive interrupts according to claim 6 wherein the controller device is a system bus adapter.
Claim 11
Dependent Claim
86 words
The method to reduce receive interrupts according to claim 6 wherein the step of determining whether the receive interrupt should be posted to the CPU in response to the predetermined event comprises the steps of: receiving the data packet; incrementing the receive count counter by one; returning to the step of determining if the receive count counter does not equal the receive count limit variable; and posting the receive interrupt to the CPU if the receive count counter does not equal the receive count limit variable.
Claim 12
Dependent Claim
87 words
The method to reduce receive interrupts according to claim 9 wherein the step of determining whether the receive interrupt should be posted to the CPU in response to the predetermined event comprises the steps of: waiting a specified time unit; incrementing the receive count counter by one; returning to the step of determining if the receive time counter does not equal the receive time limit variable; and posting the receive interrupt to the CPU if the receive time counter does not equal the receive time limit variable.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |