Semiconductor IC device with transistors of different characteristics

Claim 2

A semiconductor device comprising: a semiconductor substrate having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first well; and a peripheral circuit for said memory cell formed in said second well.

Claim 3

A semiconductor device according to claim 1, wherein the depths of the local maximums of said first and second wells are the same, and the first conductivity type impurity concentration of the local maximum of said second well is higher by about 30% or more than that of the local maximum of said first well.

Claim 4

A semiconductor device according to claim 2, wherein the first conductivity type impurity concentration of the local maximum of said second well is higher about twice or more than that of the local maximum of said first well.

Claim 5

A semiconductor device, comprising: a semiconductor substrate having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a memory cell formed in said first well; and a peripheral circuit for said memory cell formed in said second well, wherein said first well partially overlaps said second well.

Claim 6

A semiconductor device, comprising: a semiconductor substrate having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a memory cell formed in said first well; and a peripheral circuit for said memory cell formed in said second well, wherein said first well partially overlaps said second well.

Claim 7

A semiconductor device according to claim 4, wherein said second well surrounds said first well, and the inner wall of said second well is positioned inside the outer periphery of said first well.

Claim 8

A semiconductor device, comprising: a semiconductor substrate having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher about three times or more than that of the local maximum of said first well; a memory cell formed in said first well; and a peripheral circuit for said memory cell formed in said second well.

Claim 9

A semiconductor device, comprising: a semiconductor substrate having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher about three times or more than that of the local maximum of said first well; a memory cell formed in said first well; and a peripheral circuit for said memory cell formed in said second well.

Claim 10

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a memory cell formed in said first well; a peripheral circuit for said memory cell formed in said second well; a third well and a fourth well of a second conductivity type opposite to the first conductivity type in said semiconductor substrate, said third and fourth wells including therein said first and second wells.

Claim 11

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a memory cell formed in said first well; a peripheral circuit for said memory cell formed in said second well; a third well and a fourth well of a second conductivity type opposite to the first conductivity type in said semiconductor substrate, said third and fourth wells including therein said first and second wells.

Claim 12

A semiconductor device according to claim 7, wherein said third and fourth wells form one integrated well.

Claim 13

A semiconductor device according to claim 8, wherein said peripheral circuit in said second well includes a sense amplifier circuit.

Claim 14

A semiconductor device according to claim 7, wherein said peripheral circuit in said second well includes a word line drive circuit or an input/output circuit.

Claim 15

A semiconductor device according to claim 7, wherein said memory cell and said peripheral circuit each have source/drain regions of the same conductivity type, and a punch-through voltage between the source/drain regions of said peripheral circuit and said fourth well is larger than a punch-through voltage between the source/drain regions of said memory cell and said third well.

Claim 16

A semiconductor device according to claim 7, wherein the local maximums of said first and second wells are at a depth position of 0.5 μm-0.7 μm from the one surface of said semiconductor substrate.

Claim 17

A semiconductor device comprising: a semiconductor substrate having one surface; a first retrograde well and a second retrograde well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, an impurity concentration of a local maximum of said second retrograde well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first retrograde well; and a peripheral circuit for said memory cell formed in said second retrograde well.

Claim 18

A semiconductor device comprising: a semiconductor substrate having one surface; a first retrograde well and a second retrograde well respectively formed in a first region and a second region in areas of the one surface of said semiconductor substrate, an impurity concentration of a local maximum of said second retrograde well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first retrograde well; and a peripheral circuit for said memory cell formed in said second retrograde well.

Claim 19

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first well and a second well formed in said semiconductor substrate and being of a second conductivity type opposite to the first conductivity type; a third well and a fourth well respectively formed in said first and second wells and being of the first conductivity type; and a first MOS transistor and a second MOS transistor respectively formed in said third and fourth wells and having first source/drain regions and second source/drain regions of the second conductivity type, wherein said first MOS transistor constitutes a transfer transistor of a memory cell, said second MOS transistor constitutes a peripheral circuit of the memory cell, first conductivity type impurity concentration distributions of said third and fourth wells each have a local maximum at a depth position apart from a surface of said semiconductor substrate, and a punch-through voltage between the first source/drain regions and said first well is set lower than a punch-through voltage between the second source/drain regions and said second well.

Claim 20

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first well and a second well formed in said semiconductor substrate and being of a second conductivity type opposite to the first conductivity type; a third well and a fourth well respectively formed in said first and second wells and being of the first conductivity type; and a first MOS transistor and a second MOS transistor respectively formed in said third and fourth wells and having first source/drain regions and second source/drain regions of the second conductivity type, wherein said first MOS transistor constitutes a transfer transistor of a memory cell, said second MOS transistor constitutes a peripheral circuit of the memory cell, first conductivity type impurity concentration distributions of said third and fourth wells each have a local maximum at a depth position apart from a surface of said semiconductor substrate, and a punch-through voltage between the first source/drain regions and said first well is set lower than a punch-through voltage between the second source/drain regions and said second well.

Claim 21

A semiconductor device according to claim 14, wherein said first and second wells form one integrated well.

Claim 22

A semiconductor device according to claim 15, wherein said fourth well partially overlaps said third well, and the remaining region of said third well is divided into a plurality of sub-regions.

Claim 23

A semiconductor device comprising: a semiconductor substrate having one surface; a first well and a second well of a first conductivity type respectively formed in a first region and a second region in areas of a second opposite conductivity type in the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first well; and a peripheral circuit for said memory cell formed in said second well.

Claim 24

A semiconductor device comprising: a semiconductor substrate having one surface; a first well and a second well of a first conductivity type respectively formed in a first region and a second region in areas of a second opposite conductivity type in the one surface of said semiconductor substrate, said first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of said semiconductor substrate, and the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first well; and a peripheral circuit for said memory cell formed in said second well.

Claim 25

A semiconductor device according to claim 17, wherein the depths of the local maximums of said first and second wells are the same, and the first conductivity type impurity concentration of the local maximum of said second well is higher by about 30% or more than that of the local maximum of said first well.

Claim 26

A semiconductor device according to claim 18, wherein the first conductivity type impurity concentration of the local maximum of said second well is higher about twice or more than that of the local maximum of said first well.

Claim 27

A semiconductor device comprising: a semiconductor substrate having one surface; a first retrograde well and a second retrograde well of a first conductivity type respectively formed in a first region and a second region in areas of an second opposite conductivity type in the one surface of said semiconductor substrate, the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first retrograde well; and a peripheral circuit for said memory cell formed in said second retrograde well.

Claim 28

A semiconductor device comprising: a semiconductor substrate having one surface; a first retrograde well and a second retrograde well of a first conductivity type respectively formed in a first region and a second region in areas of an second opposite conductivity type in the one surface of said semiconductor substrate, the first conductivity type impurity concentration of the local maximum of said second well is higher than that of said first well; a dynamic random access memory cell, which does not have a floating gate, formed in said first retrograde well; and a peripheral circuit for said memory cell formed in said second retrograde well.