US5933157A
Expired / Lapsed
US
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Central processing unit with integrated graphics functions
Assignee: Sun Microsystems Inc
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Filing: 1996-04-19
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Granted: 1999-08-03
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Expires: 2016-04-19
Abstract
Abstract The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category. Furthermore, under this embodiment, the IEU is also used to execute a number of graphics data edge handling and 3-D array addressing operations, while the load and store unit (LSU) of the CPU is also used to execute a number of graphics data load and store operations, including conditional store operations.
Inventors
- 👤 Timothy J. Van Hook
- 👤 Leslie Dean Kohn
- 👤 Robert Yung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:01
CPC Classifications
G; G06; G06F; G06F15/00; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F17/00; G06F17/10; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
116 words
A microprocessor with graphics operations capabilities, comprising: a first memory location configured to store information corresponding to a first plurality of packed pixels; a second memory location configured to store information corresponding to a second plurality of packed pixels; comparison logic, coupled to said first and second memory locations, configured to compare in parallel each of said first plurality of packed pixels with corresponding ones of said second plurality of packed pixels; and said comparison logic generating a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels.
Claim 2
Dependent Claim
116 words
A microprocessor with graphics operations capabilities, comprising: a first memory location configured to store information corresponding to a first plurality of packed pixels; a second memory location configured to store information corresponding to a second plurality of packed pixels; comparison logic, coupled to said first and second memory locations, configured to compare in parallel each of said first plurality of packed pixels with corresponding ones of said second plurality of packed pixels; and said comparison logic generating a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels.
Claim 3
Dependent Claim
19 words
The microprocessor of claim 1 wherein said comparison logic is configured to determine if said pixel information is equal.
Claim 4
Dependent Claim
33 words
The microprocessor of claim 1 wherein said comparison logic is configured to determine if said pixel information in said first memory location is greater than said pixel information in said second memory location.
Claim 5
Dependent Claim
20 words
The microprocessor of claim 1 wherein at least one of said memory locations is a register in a register file.
Claim 6
Dependent Claim
15 words
The microprocessor of claim 4 wherein said register file is a floating point register file.
Claim 7
Dependent Claim
14 words
The microprocessor of claim 1 wherein each of said pixel representations is 16 bits.
Claim 8
Dependent Claim
14 words
The microprocessor of claim 1 wherein each of said pixel representations is 32 bits.
Claim 9
Dependent Claim
17 words
The microprocessor of claim 1 wherein said mask includes at least one bit for each pixel comparison.
Claim 10
Dependent Claim
28 words
The microprocessor of claim 1 further comprising: selection logic, coupled to receive said mask as an input, for selecting among a plurality of pixel information using said mask.
Claim 11
Dependent Claim
201 words
A microprocessor with graphics operations capabilities, comprising: a first memory location configured to store information corresponding to a first plurality of packed pixels; a second memory location configured to store information corresponding to a second plurality of packed pixels; comparison logic, coupled to said first and second memory locations, configured to compare in parallel each of said first plurality of packed pixels with a corresponding one of said second plurality of packed pixels, and generate a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels, wherein said comparison logic is configured to determine at least whether said pixel information is equal and whether said pixel information in said first memory location is greater than said pixel information in said second memory location; selection logic, coupled to receive said mask as an input, for selecting among a plurality of pixel information using said mask; wherein at least one of said memory locations is a register in a floating point register file; and wherein said mask includes a single bit for each multi-pixel comparison.
Claim 12
Dependent Claim
201 words
A microprocessor with graphics operations capabilities, comprising: a first memory location configured to store information corresponding to a first plurality of packed pixels; a second memory location configured to store information corresponding to a second plurality of packed pixels; comparison logic, coupled to said first and second memory locations, configured to compare in parallel each of said first plurality of packed pixels with a corresponding one of said second plurality of packed pixels, and generate a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels, wherein said comparison logic is configured to determine at least whether said pixel information is equal and whether said pixel information in said first memory location is greater than said pixel information in said second memory location; selection logic, coupled to receive said mask as an input, for selecting among a plurality of pixel information using said mask; wherein at least one of said memory locations is a register in a floating point register file; and wherein said mask includes a single bit for each multi-pixel comparison.
Claim 13
Dependent Claim
14 words
The microprocessor of claim 10 wherein each of said pixel representations is 16 bits.
Claim 14
Dependent Claim
14 words
The microprocessor of claim 10 wherein each of said pixel representations is 32 bits.
Claim 15
Dependent Claim
137 words
A computer system comprising: a main memory; a bus coupled to said main memory; a microprocessor with graphics operations capabilities coupled to said bus, said microprocessor including a first memory location configured to store information corresponding to a first plurality of packed pixels; a second memory location configured to store information corresponding to a second plurality of packed pixels; comparison logic, coupled to said first and second memory locations, configured to compare in parallel each of said first plurality of packed pixels with a corresponding one of said second plurality of packed pixels; and said comparison logic generating a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels.
Claim 16
Dependent Claim
137 words
A computer system comprising: a main memory; a bus coupled to said main memory; a microprocessor with graphics operations capabilities coupled to said bus, said microprocessor including a first memory location configured to store information corresponding to a first plurality of packed pixels; a second memory location configured to store information corresponding to a second plurality of packed pixels; comparison logic, coupled to said first and second memory locations, configured to compare in parallel each of said first plurality of packed pixels with a corresponding one of said second plurality of packed pixels; and said comparison logic generating a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels.
Claim 17
Dependent Claim
20 words
The computer system of claim 13 wherein said comparison logic is configured to determine if said pixel information is equal.
Claim 18
Dependent Claim
34 words
The computer system of claim 13 wherein said comparison logic is configured to determine if said pixel information in said first memory location is greater than said pixel information in said second memory location.
Claim 19
Dependent Claim
21 words
The computer system of claim 13 wherein at least one of said memory locations is a register in a register file.
Claim 20
Dependent Claim
16 words
The computer system of claim 16 wherein said register file is a floating point register file.
Claim 21
Dependent Claim
15 words
The computer system of claim 13 wherein each of said pixel representations is 16 bits.
Claim 22
Dependent Claim
15 words
The computer system of claim 13 wherein each of said pixel representations is 32 bits.
Claim 23
Dependent Claim
18 words
The computer system of claim 13 wherein said mask includes at least one bit for each pixel comparison.
Claim 24
Dependent Claim
29 words
The computer system of claim 13 further comprising: selection logic, coupled to receive said mask as an input, for selecting among a plurality of pixel information using said mask.
Claim 25
Independent Claim
116 words
A method for operating a microprocessor with graphics operations capabilities, comprising the steps of: storing information corresponding to a first plurality of packed pixels in a first memory location; storing information corresponding to a second plurality of packed pixels in a second memory location; comparing in parallel said information corresponding to each of said first plurality of packed pixels with information for a corresponding one of said second plurality of packed pixels; generating a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels; and storing said mask.
Claim 26
Independent Claim
116 words
A method for operating a microprocessor with graphics operations capabilities, comprising the steps of: storing information corresponding to a first plurality of packed pixels in a first memory location; storing information corresponding to a second plurality of packed pixels in a second memory location; comparing in parallel said information corresponding to each of said first plurality of packed pixels with information for a corresponding one of said second plurality of packed pixels; generating a mask corresponding to a result of said comparison, said mask having an entry for each pixel in said first memory location, each mask entry having fewer bits than a number of bits representing each of said packed pixels; and storing said mask.
Claim 27
Dependent Claim
17 words
The method of claim 22 wherein said comparing step includes determining if said pixel information is equal.
Claim 28
Dependent Claim
31 words
The method of claim 22 wherein said comparing step includes determining if said pixel information in said first memory location is greater than said pixel information in said second memory location.
Claim 29
Dependent Claim
20 words
The method of claim 22 wherein at least one of said memory locations is a register in a register file.
Claim 30
Dependent Claim
17 words
The method of claim 22 wherein said mask includes at least one bit for each pixel comparison.
Claim 31
Dependent Claim
20 words
The method of claim 22 further comprising the step of: selecting among a plurality of pixel information using said mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |