US5157388A
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Method and apparatus for graphics data interpolation
Assignee: Intel Corp
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Filing: 1991-04-02
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Granted: 1992-10-20
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Expires: 2011-04-02
Abstract
Abstract Special purpose graphics instructions are provided to implement linear interpolation of pixel attributes such as a distance (Z) value or color intensity. Multiple fixed-point real number additions are performed in parallel in a 64-bit adder. The real number sums are truncated upon being loaded in a MERGE register, the contents of which are then shifted. By performing two or more of such instructions consecutively, multiple interpolated values are accumulated in the MERGE register.
Inventors
- 👤 Leslie D. Kohn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:34
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/17; G09; G09G; G09G5/00; G09G5/02; G09G5/026
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
239 words
In a digital processor for generating display data for rendering a graphical representation of an object on a display screen, said display screen comprising a plurality of pixels, said digital processor sequentially performing operations in synchronism with a clock signal, a method for interpolating a pixel attribute comprising the steps of: (a) providing a MERGE register having a plurality of bits divisible into a plurality of consecutive fields of plural bits; (b) retrieving a plurality of data words representing a selected attribute of a plurality of corresponding pixels, each of said data words representing a fixed point real number and having an integer portion represented by N i bits and a fractional portion represented by N f bits; (c) concurrently adding a predetermined interpolation constant to each of said plurality of data words, thereby providing a plurality of fixed point real number sums; (d) truncating each of the plurality of fixed point real number sums to an integer value with N i bits; (e) concurrently loading each of said plurality of truncated sums into respective non-adjacent fields of N i bits of said MERGE register; (f) shifting said MERGE register by N i bits so as to shift the contents of the MERGE register field by field; wherein steps (b), (c), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; and (g) repeating steps (b)-(e) to accumulate interleaved successive pluralities of truncated sums.
Claim 2
Dependent Claim
239 words
In a digital processor for generating display data for rendering a graphical representation of an object on a display screen, said display screen comprising a plurality of pixels, said digital processor sequentially performing operations in synchronism with a clock signal, a method for interpolating a pixel attribute comprising the steps of: (a) providing a MERGE register having a plurality of bits divisible into a plurality of consecutive fields of plural bits; (b) retrieving a plurality of data words representing a selected attribute of a plurality of corresponding pixels, each of said data words representing a fixed point real number and having an integer portion represented by N i bits and a fractional portion represented by N f bits; (c) concurrently adding a predetermined interpolation constant to each of said plurality of data words, thereby providing a plurality of fixed point real number sums; (d) truncating each of the plurality of fixed point real number sums to an integer value with N i bits; (e) concurrently loading each of said plurality of truncated sums into respective non-adjacent fields of N i bits of said MERGE register; (f) shifting said MERGE register by N i bits so as to shift the contents of the MERGE register field by field; wherein steps (b), (c), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; and (g) repeating steps (b)-(e) to accumulate interleaved successive pluralities of truncated sums.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein said pixel attribute represents a distance from a corresponding point on said object to said display screen.
Claim 4
Dependent Claim
16 words
The method of claim 2 wherein said plurality of data words are retrieved from a Z-buffer.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein said pixel attribute represents a color intensity.
Claim 6
Dependent Claim
214 words
In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for interpolating data values represented by said data words comprising the steps of: (a) providing a MERGE register having a plurality of bits divisible into a plurality of consecutive fields of plural bits; (b) retrieving a plurality of said data words, each of said data words representing a fixed point real number and having an integer portion represented by N i bits and a fractional portion represented by N f bits; (c) concurrently adding a predetermined interpolation constant to each of said plurality of data words, thereby providing a plurality of fixed point real number sums; (d) truncating each of the plurality of fixed point real number sums to an integer value with N i bits; (e) concurrently loading each of said plurality of truncated sums into respective non-adjacent fields of N i bits of said MERGE register; (f) shifting said MERGE register by N i bits so as to shift the contents of the MERGE register field by field; wherein steps (b), (c), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; and (g) repeating steps (b)-(e) to accumulate interleaved successive pluralities of truncated sums.
Claim 7
Dependent Claim
214 words
In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for interpolating data values represented by said data words comprising the steps of: (a) providing a MERGE register having a plurality of bits divisible into a plurality of consecutive fields of plural bits; (b) retrieving a plurality of said data words, each of said data words representing a fixed point real number and having an integer portion represented by N i bits and a fractional portion represented by N f bits; (c) concurrently adding a predetermined interpolation constant to each of said plurality of data words, thereby providing a plurality of fixed point real number sums; (d) truncating each of the plurality of fixed point real number sums to an integer value with N i bits; (e) concurrently loading each of said plurality of truncated sums into respective non-adjacent fields of N i bits of said MERGE register; (f) shifting said MERGE register by N i bits so as to shift the contents of the MERGE register field by field; wherein steps (b), (c), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; and (g) repeating steps (b)-(e) to accumulate interleaved successive pluralities of truncated sums.
Claim 8
Dependent Claim
186 words
In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for interpolating data values represented by said data words comprising the steps of: (a) providing a MERGE register having a plurality of bits divisible into a plurality of consecutive fields of plural bits; (b) retrieving a plurality of said data words, each of said data words comprising a predetermined number of bits N; (c) concurrently adding a predetermined interpolation constant to each of said plurality of data words, thereby providing a plurality of sums; (d) truncating each of the plurality of sums to a value with M bits, where 1<M<N; (e) concurrently loading each of said plurality of truncated sums into respective non-adjacent fields of M bits of said MERGE register; (f) shifting said MERGE register by M bits so as to shift the contents of the MERGE register field by field; wherein steps (b), (c), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; and (g) repeating steps (b)-(e) to accumulate interleaved successive pluralities of truncated sums.
Claim 9
Dependent Claim
186 words
In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for interpolating data values represented by said data words comprising the steps of: (a) providing a MERGE register having a plurality of bits divisible into a plurality of consecutive fields of plural bits; (b) retrieving a plurality of said data words, each of said data words comprising a predetermined number of bits N; (c) concurrently adding a predetermined interpolation constant to each of said plurality of data words, thereby providing a plurality of sums; (d) truncating each of the plurality of sums to a value with M bits, where 1<M<N; (e) concurrently loading each of said plurality of truncated sums into respective non-adjacent fields of M bits of said MERGE register; (f) shifting said MERGE register by M bits so as to shift the contents of the MERGE register field by field; wherein steps (b), (c), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; and (g) repeating steps (b)-(e) to accumulate interleaved successive pluralities of truncated sums.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |