US5081698A
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Method and apparatus for graphics display data manipulation
Assignee: Intel Corp
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Filing: 1989-02-14
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Granted: 1992-01-14
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Expires: 2009-02-14
Abstract
Abstract Special purpose graphics instructions are provided to facilitate hidden surface elimination. A Z-buffer check instruction performs multiple, simultaneous unsigned-integer (ordinal) comparisons of newly computed distance (Z) values with the contents of a Z-buffer. Distances of points to be drawn are compared with corresponding values in the Z-buffer, and appropriate bits of a pixel mask are then set to designate those pixels for which the points to be drawn are closer (smaller) than the Z-buffer values. Previously calculated bits of the pixel mask are shifted so that consecutive Z-buffer check instructions accumulate their results in the pixel mask register. A pixel store instruction utilizes the pixel mask to update only those pixel locations in a frame buffer which correspond to a point on a newly rendered surface closer than the surface represented by the current pixel value.
Inventors
- 👤 Leslie D. Kohn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:16
CPC Classifications
G; G09; G09B; G09B9/00; G09B9/02; G09B9/08; G09B9/30; G09B9/301; G06; G06T; G06T15/00; G06T15/10; G06T15/40; G06T15/405; G06T15/50; G06T15/80; G06T15/87
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
256 words
In a digital processor for generating display data for rendering a graphical representation of a three dimensional object on a display screen, said display screen comprising a plurality of pixels, said digital processor sequentially performing operations in synchronism with a clock signal, a method for selectively designating a pixel to be updated comprising the steps of: (a) storing a plurality of first Z-values in a Z-buffer, each such first Z-value corresponding to one of said pixels and representing a distance from a reference plane to a corresponding point of a first three dimensional object rendered on said display screen; (b) designating a register to store a pixel mask comprising a plurality of bits, each such bit corresponding to one of said pixels; (c) for each pixel corresponding to a point on a second three-dimensional object to be rendered on said display screen, computing and storing a corresponding second Z-value; (d) shifting said pixel mask by a predetermined number of bits N; (e) selecting N of said second Z-values; (f) comparing said N second Z-values with N corresponding first Z-values retrieved from said Z-buffer; (g) setting a corresponding i th bit of said pixel mask if an i th one of said N second Z-values is not greater than said corresponding first Z-value retrieved from said Z-buffer; and (h) storing the smaller of said i th second Z-value and said corresponding first Z-value retrieved from said Z-buffer; wherein steps (d), (e), (f), (g) and (h) are performed substantially concurrently during a single cycle of said clock signal.
Claim 2
Dependent Claim
256 words
In a digital processor for generating display data for rendering a graphical representation of a three dimensional object on a display screen, said display screen comprising a plurality of pixels, said digital processor sequentially performing operations in synchronism with a clock signal, a method for selectively designating a pixel to be updated comprising the steps of: (a) storing a plurality of first Z-values in a Z-buffer, each such first Z-value corresponding to one of said pixels and representing a distance from a reference plane to a corresponding point of a first three dimensional object rendered on said display screen; (b) designating a register to store a pixel mask comprising a plurality of bits, each such bit corresponding to one of said pixels; (c) for each pixel corresponding to a point on a second three-dimensional object to be rendered on said display screen, computing and storing a corresponding second Z-value; (d) shifting said pixel mask by a predetermined number of bits N; (e) selecting N of said second Z-values; (f) comparing said N second Z-values with N corresponding first Z-values retrieved from said Z-buffer; (g) setting a corresponding i th bit of said pixel mask if an i th one of said N second Z-values is not greater than said corresponding first Z-value retrieved from said Z-buffer; and (h) storing the smaller of said i th second Z-value and said corresponding first Z-value retrieved from said Z-buffer; wherein steps (d), (e), (f), (g) and (h) are performed substantially concurrently during a single cycle of said clock signal.
Claim 3
Dependent Claim
7 words
The method of claim 1 wherein N=2.
Claim 4
Dependent Claim
11 words
The method of claim 2 wherein each Z-value comprises 32 bits.
Claim 5
Dependent Claim
7 words
The method of claim 1 wherein N=4.
Claim 6
Dependent Claim
11 words
The method of claim 4 wherein each Z-value comprises 16 bits.
Claim 7
Dependent Claim
107 words
The method of claim 1 further comprising the steps of: (i) providing a frame buffer for storing a plurality of first pixel values, each such first pixel value representing an attribute of said first object rendered on said display screen; (j) for each pixel corresponding to a point on said second object to be rendered on said display screen, computing and storing a corresponding second pixel value; (k) selecting M of said second pixel values; and (l) storing a subset of said M second pixel values in corresponding locations of said frame buffer, said subset determined by the logical value of corresponding bits of said pixel mask.
Claim 8
Dependent Claim
17 words
The method of claim 6 wherein each of said pixel values represents at least one color intensity.
Claim 9
Dependent Claim
16 words
The method of claim 6 wherein each of said pixel values represents three independent color intensities.
Claim 10
Dependent Claim
7 words
The method of claim 6 wherein M=8.
Claim 11
Dependent Claim
12 words
The method of claim 9 wherein each pixel value comprises 8 bits.
Claim 12
Dependent Claim
7 words
The method of claim 6 wherein M=4.
Claim 13
Dependent Claim
12 words
The method of claim 11 wherein each pixel value comprises 16 bits.
Claim 14
Dependent Claim
7 words
The method of claim 6 wherein M=2.
Claim 15
Dependent Claim
12 words
The method of claim 13 wherein each pixel value comprises 32 bits.
Claim 16
Dependent Claim
232 words
In a digital processor for generating display data for rendering a graphical representation of a three dimensional object on a display screen, said display screen comprising a plurality of pixels, an apparatus for selectively updating said pixels comprising: (a) first register means for storing a plurality of first Z-values, each such first Z-value corresponding to one of said pixels and representing a distance from a reference plane to a corresponding point of a first three-dimensional object rendered on said display screen; (b) second register means for storing a plurality of second Z-values, each such second Z-value corresponding to one of said pixels and representing a distance from said reference plane to a corresponding point of a second three-dimensional object to be rendered on said display screen; (c) comparator means for comparing N of said first Z-values with N corresponding second Z-values; (d) pixel mask means having at least N-bits, each bit for storing a result of a corresponding one of said comparisons between said first and second Z-values; (e) frame buffer means for storing a plurality of first pixel values representing said first object; (f) third register means for storing a plurality of second pixel values representing said second object; and (g) data path means for selectively storing in said frame buffer means corresponding ones of said second pixel values as a function of a corresponding bit of said pixel mask means.
Claim 17
Dependent Claim
232 words
In a digital processor for generating display data for rendering a graphical representation of a three dimensional object on a display screen, said display screen comprising a plurality of pixels, an apparatus for selectively updating said pixels comprising: (a) first register means for storing a plurality of first Z-values, each such first Z-value corresponding to one of said pixels and representing a distance from a reference plane to a corresponding point of a first three-dimensional object rendered on said display screen; (b) second register means for storing a plurality of second Z-values, each such second Z-value corresponding to one of said pixels and representing a distance from said reference plane to a corresponding point of a second three-dimensional object to be rendered on said display screen; (c) comparator means for comparing N of said first Z-values with N corresponding second Z-values; (d) pixel mask means having at least N-bits, each bit for storing a result of a corresponding one of said comparisons between said first and second Z-values; (e) frame buffer means for storing a plurality of first pixel values representing said first object; (f) third register means for storing a plurality of second pixel values representing said second object; and (g) data path means for selectively storing in said frame buffer means corresponding ones of said second pixel values as a function of a corresponding bit of said pixel mask means.
Claim 18
Dependent Claim
13 words
The apparatus of claim 15 wherein said pixel mask means comprises 8 bits.
Claim 19
Dependent Claim
15 words
The apparatus of claim 16 wherein said apparatus is included in a single chip microprocessor.
Claim 20
Dependent Claim
203 words
In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for selectively designating a data word to be updated comprising the steps of: (a) storing a plurality of first data words in a first memory means, said first data words representing respective first data values; (b) designating a register to store a mask comprising a plurality of bits, each such bit corresponding to one of said first data words; (c) for each of a designated subset of said first data words, computing and storing a corresponding updated first data value; (d) shifting said mask register by a predetermined number of bits N; (e) selecting N of said updated first data values; (f) comparing said N updated first data values with N corresponding first data words retrieved from said first memory means; and (g) setting a corresponding i th bit of said mask register if an i th one of said N updated first data values has a predetermined mathematical relationship to said corresponding first data word retrieved from said first memory means; wherein steps (d), (e), (f), and (g) are performed substantially concurrently during a single cycle of said clock signal.
Claim 21
Dependent Claim
203 words
In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for selectively designating a data word to be updated comprising the steps of: (a) storing a plurality of first data words in a first memory means, said first data words representing respective first data values; (b) designating a register to store a mask comprising a plurality of bits, each such bit corresponding to one of said first data words; (c) for each of a designated subset of said first data words, computing and storing a corresponding updated first data value; (d) shifting said mask register by a predetermined number of bits N; (e) selecting N of said updated first data values; (f) comparing said N updated first data values with N corresponding first data words retrieved from said first memory means; and (g) setting a corresponding i th bit of said mask register if an i th one of said N updated first data values has a predetermined mathematical relationship to said corresponding first data word retrieved from said first memory means; wherein steps (d), (e), (f), and (g) are performed substantially concurrently during a single cycle of said clock signal.
Claim 22
Dependent Claim
34 words
The method of claim 18 further comprising, after step (g), the step of: (h) storing said i th updated first data value in said corresponding first data word as a function of said comparison.
Claim 23
Dependent Claim
108 words
The method of claim 18 further comprising the steps of: (h) storing a plurality of second data words in a second memory means, said second data words representing respective second data values, said second data words being logically associated with said first data words; (i) for each of a designated subset of said second data words, computing and storing a corresponding updated second data value; (j) selecting M of said updated second data values; and (k) storing selected ones of said M updated second data values in corresponding locations of said second memory means, such selection determined by the logical value of corresponding bits of said mask register.
Claim 24
Dependent Claim
175 words
In a digital processor for performing operations on a plurality of data words, an apparatus for selectively updating one of said data words comprising; (a) first memory means for storing a plurality of first data words representing first data values; (b) first register means for storing a plurality of updated first data values; (c) comparator means for comparing N of said first data words with N corresponding updated first data values; (d) mask means having at least N-bits, each bit for storing a result of a corresponding one of said comparisons between said first data words and said updated first data values; (e) second memory means for storing a plurality of second data words representing second data values, said second data words being logically associated with said first data words; (f) second register means for storing a plurality of updated second data values; and (g) data path means for selectively storing in said second memory means corresponding ones of said updated second data values as a function of a corresponding bit of said mask means.
Claim 25
Dependent Claim
175 words
In a digital processor for performing operations on a plurality of data words, an apparatus for selectively updating one of said data words comprising; (a) first memory means for storing a plurality of first data words representing first data values; (b) first register means for storing a plurality of updated first data values; (c) comparator means for comparing N of said first data words with N corresponding updated first data values; (d) mask means having at least N-bits, each bit for storing a result of a corresponding one of said comparisons between said first data words and said updated first data values; (e) second memory means for storing a plurality of second data words representing second data values, said second data words being logically associated with said first data words; (f) second register means for storing a plurality of updated second data values; and (g) data path means for selectively storing in said second memory means corresponding ones of said updated second data values as a function of a corresponding bit of said mask means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-13 | 1995-07-15 | 1996-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-13 | 1999-07-15 | 2000-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-13 | 2003-07-15 | 2004-01-14 | $7700.00 | Window Closed / Lapsed |