Multiple interrupt controller and control method using an intelligent priority-decision mechanism

Claim 1

A multiple interrupt controller using an intelligent priority-decision mechanism, comprising: an interrupt detector for detecting interrupts generated by local interrupt resources; a total interrupt counter operatively connected to said interrupt detector for counting and representing a total interrupt number detected at said interrupt detector; a plurality of individual interrupt counters for counting a number of said interrupts generated by each one of said local interrupt resources; an interrupt flag operatively connected to said interrupt detector for being set when an interrupt corresponding to said interrupt flag is detected from said interrupt detector; an encoder and a priority decision device operatively connected to said interrupt detector, said individual interrupt counters, and said total interrupt counter for encoding interrupt information and deciding a priority for each of said interrupts using information from said total interrupt counter and said plurality of individual interrupt counters as a basic factor; an interrupt queue controller comprising a queue counter, and operatively connected to said interrupt detector for receiving a queue input request from said interrupt detector, and a queue shift request from said interrupt queue output controller, controlling an interrupt queue, and addressing the queue; an interrupt queue output controller operatively connected to said interrupt queue controller for receiving a request from a host system to output an O-th queue of the interrupt queue to said host system via a Pended bus, and simultaneously requesting a queue shift for said interrupt queue controller; and said interrupt queue operatively connected to said encoder and priority decision device, said interrupt queue controller, and said interrupt queue output controller for preserving temporary interrupts to be shifted when receiving said queue shift request from said interrupt queue output controller.

Claim 3

A method of controlling multiple interrupts using an intelligent priority-decision mechanism, comprising the steps of; a. repeatedly confirming whether an interrupt has been detected; b. checking whether the number of the detected interrupt is more than one if an interrupt has been detected at said step a.; c. setting a flag corresponding to the detected interrupt if the number of the detected interrupt is one in steps b.; d. encoding the detected interrupt after step c.; e. requesting a queue input from the interrupt queue controller after step d.; f. confirming the queue input; g. resetting the flag corresponding to the detected interrupt and returning to step a. when receiving a queue input confirmation signal in step f.; h. setting a total interrupt counter if the number of the detected interrupt is greater than one in step b., i. setting a corresponding priority flag after step h.; j. setting an individual interrupt counter after step i.; k. encoding the detected interrupt after step j.; l. requesting a queue input from the interrupt queue controller after step k.; m. confirming the queue input after step l.; and n. resetting flag corresponding to the detected interrupt when receiving a queue input confirmation signal in step m. and returning to step a.

Claim 4

A method of controlling multiple interrupts using an intelligent priority-decision mechanism, comprising the steps of; a. repeatedly confirming whether an interrupt has been detected; b. checking whether the number of the detected interrupt is more than one if an interrupt has been detected at said step a.; c. setting a flag corresponding to the detected interrupt if the number of the detected interrupt is one in steps b.; d. encoding the detected interrupt after step c.; e. requesting a queue input from the interrupt queue controller after step d.; f. confirming the queue input; g. resetting the flag corresponding to the detected interrupt and returning to step a. when receiving a queue input confirmation signal in step f.; h. setting a total interrupt counter if the number of the detected interrupt is greater than one in step b., i. setting a corresponding priority flag after step h.; j. setting an individual interrupt counter after step i.; k. encoding the detected interrupt after step j.; l. requesting a queue input from the interrupt queue controller after step k.; m. confirming the queue input after step l.; and n. resetting flag corresponding to the detected interrupt when receiving a queue input confirmation signal in step m. and returning to step a.

Claim 5

A method of controlling multiple interrupts using an intelligent priority-decision mechanism, comprising the steps of: a. repeatedly confirming at an interrupt queue controller whether a queue input request from an interrupt detector or a queue output request from a host system has been received by said interrupt queue controller; b. checking whether the queue is empty or not if the queue input request is received in step a.; c. inputting to a queue corresponding to a value of a present queue counter if there is an empty queue in step b. d. generating a queue input confirmation signal after step c.; e. increasing the value of the queue counter by 1 and returning to step a. after step d.; f. requesting an interrupt queue shift by said interrupt queue output controller if the queue output request is received in step a.; g. confirming a queue counter by said interrupt queue controller after step f.; h. decreasing the value of the queue counter by 1 after step g. if the value of the queue counter is 1 at step a. and returning to step a., and right shifting the queue by 1, decreasing the value of the queue counter by 1 and returning to said step a. after step g. if the value of the queue counter is not equal to 1.

Claim 6

A method of controlling multiple interrupts using an intelligent priority-decision mechanism, comprising the steps of: a. repeatedly confirming at an interrupt queue controller whether a queue input request from an interrupt detector or a queue output request from a host system has been received by said interrupt queue controller; b. checking whether the queue is empty or not if the queue input request is received in step a.; c. inputting to a queue corresponding to a value of a present queue counter if there is an empty queue in step b. d. generating a queue input confirmation signal after step c.; e. increasing the value of the queue counter by 1 and returning to step a. after step d.; f. requesting an interrupt queue shift by said interrupt queue output controller if the queue output request is received in step a.; g. confirming a queue counter by said interrupt queue controller after step f.; h. decreasing the value of the queue counter by 1 after step g. if the value of the queue counter is 1 at step a. and returning to step a., and right shifting the queue by 1, decreasing the value of the queue counter by 1 and returning to said step a. after step g. if the value of the queue counter is not equal to 1.